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2019-08-16Include sysemu/reset.h a lot lessMarkus Armbruster
In my "build everything" tree, changing sysemu/reset.h triggers a recompile of some 2600 out of 6600 objects (not counting tests and objects that don't depend on qemu/osdep.h). The main culprit is hw/hw.h, which supposedly includes it for convenience. Include sysemu/reset.h only where it's needed. Touching it now recompiles less than 200 objects. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190812052359.30071-9-armbru@redhat.com>
2019-08-16Include generated QAPI headers lessMarkus Armbruster
Some of the generated qapi-types-MODULE.h are included all over the place. Changing a QAPI type can trigger massive recompiling. Top scorers recompile more than 1000 out of some 6600 objects (not counting tests and objects that don't depend on qemu/osdep.h): 6300 qapi/qapi-builtin-types.h 5700 qapi/qapi-types-run-state.h 3900 qapi/qapi-types-common.h 3300 qapi/qapi-types-sockets.h 3000 qapi/qapi-types-misc.h 3000 qapi/qapi-types-crypto.h 3000 qapi/qapi-types-job.h 3000 qapi/qapi-types-block-core.h 2800 qapi/qapi-types-block.h 1300 qapi/qapi-types-net.h Clean up headers to include generated QAPI headers only where needed. Impact is negligible except for hw/qdev-properties.h. This header includes qapi/qapi-types-block.h and qapi/qapi-types-misc.h. They are used only in expansions of property definition macros such as DEFINE_PROP_BLOCKDEV_ON_ERROR() and DEFINE_PROP_OFF_AUTO(). Moving their inclusion from hw/qdev-properties.h to the users of these macros avoids pointless recompiles. This is how other property definition macros, such as DEFINE_PROP_NETDEV(), already work. Improves things for some of the top scorers: 3600 qapi/qapi-types-common.h 2800 qapi/qapi-types-sockets.h 900 qapi/qapi-types-misc.h 2200 qapi/qapi-types-crypto.h 2100 qapi/qapi-types-job.h 2100 qapi/qapi-types-block-core.h 270 qapi/qapi-types-block.h Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190812052359.30071-3-armbru@redhat.com>
2019-08-16include: Make headers more self-containedMarkus Armbruster
Back in 2016, we discussed[1] rules for headers, and these were generally liked: 1. Have a carefully curated header that's included everywhere first. We got that already thanks to Peter: osdep.h. 2. Headers should normally include everything they need beyond osdep.h. If exceptions are needed for some reason, they must be documented in the header. If all that's needed from a header is typedefs, put those into qemu/typedefs.h instead of including the header. 3. Cyclic inclusion is forbidden. This patch gets include/ closer to obeying 2. It's actually extracted from my "[RFC] Baby steps towards saner headers" series[2], which demonstrates a possible path towards checking 2 automatically. It passes the RFC test there. [1] Message-ID: <87h9g8j57d.fsf@blackfin.pond.sub.org> https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html [2] Message-Id: <20190711122827.18970-1-armbru@redhat.com> https://lists.nongnu.org/archive/html/qemu-devel/2019-07/msg02715.html Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20190812052359.30071-2-armbru@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-08-02target/arm: Avoid bogus NSACR traps on M-profile without Security ExtensionPeter Maydell
In Arm v8.0 M-profile CPUs without the Security Extension and also in v7M CPUs, there is no NSACR register. However, the code we have to handle the FPU does not always check whether the ARM_FEATURE_M_SECURITY bit is set before testing whether env->v7m.nsacr permits access to the FPU. This means that for a CPU with an FPU but without the Security Extension we would always take a bogus fault when trying to stack the FPU registers on an exception entry. We could fix this by adding extra feature bit checks for all uses, but it is simpler to just make the internal value of nsacr 0xcff ("all non-secure accesses allowed"), since this is not guest visible when the Security Extension is not present. This allows us to continue to follow the Arm ARM pseudocode which takes a similar approach. (In particular, in the v8.1 Arm ARM the register is documented as reading as 0xcff in this configuration.) Fixes: https://bugs.launchpad.net/qemu/+bug/1838475 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20190801105742.20036-1-peter.maydell@linaro.org
2019-07-30target/arm: Deliver BKPT/BRK exceptions to correct exception levelPeter Maydell
Most Arm architectural debug exceptions (eg watchpoints) are ignored if the configured "debug exception level" is below the current exception level (so for example EL1 can't arrange to get debug exceptions for EL2 execution). Exceptions generated by the BRK or BPKT instructions are a special case -- they must always cause an exception, so if we're executing above the debug exception level then we must take them to the current exception level. This fixes a bug where executing BRK at EL2 could result in an exception being taken at EL1 (which is strictly forbidden by the architecture). Fixes: https://bugs.launchpad.net/qemu/+bug/1838277 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190730132522.27086-1-peter.maydell@linaro.org
2019-07-29i386: Fix Snowridge CPU model name and featuresPaul Lai
Changing the name to Snowridge from SnowRidge-Server. There is no client model of Snowridge, so "-Server" is unnecessary. Removing CPUID_EXT_VMX from Snowridge cpu feature list. Signed-off-by: Paul Lai <paul.c.lai@intel.com> Tested-by: Tao3 Xu <tao3.xu@intel.com> Message-Id: <20190716155808.25010-1-paul.c.lai@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-07-25Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
Two more bugfix patches + 1 doc fix. # gpg: Signature made Wed 24 Jul 2019 10:22:06 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: docs: correct kconfig option i386/kvm: Do not sync nested state during runtime virtio-scsi: fixed virtio_scsi_ctx_check failed when detaching scsi disk Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-24i386/kvm: Do not sync nested state during runtimeJan Kiszka
Writing the nested state e.g. after a vmport access can invalidate important parts of the kernel-internal state, and it is not needed as well. So leave this out from KVM_PUT_RUNTIME_STATE. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Message-Id: <bdd53f40-4e60-f3ae-7ec6-162198214953@siemens.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-07-22target/mips: Fix emulation of MSA pack instructions on big endian hostsAleksandar Markovic
Fix emulation of MSA pack instructions on big endian hosts. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1563812573-30309-3-git-send-email-aleksandar.markovic@rt-rk.com>
2019-07-22target/mips: Add 'fall through' comments for handling nanoMips' SHXS, SWXSAleksandar Markovic
This was found by GCC 8.3 static analysis. Missed in commit fb32f8c8560. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <1563812573-30309-2-git-send-email-aleksandar.markovic@rt-rk.com>
2019-07-22Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20190722' into staging target-arm queue: * target/arm: Add missing break statement for Hypervisor Trap Exception (fixes handling of SMC insn taken to AArch32 Hyp mode via HCR.TSC) * hw/arm/fsl-imx6ul.c: Remove dead SMP-related code * target/arm: Limit ID register assertions to TCG * configure: Clarify URL to source downloads * contrib/elf2dmp: Build download.o with CURL_CFLAGS # gpg: Signature made Mon 22 Jul 2019 14:13:31 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190722: contrib/elf2dmp: Build download.o with CURL_CFLAGS configure: Clarify URL to source downloads target/arm: Limit ID register assertions to TCG hw/arm/fsl-imx6ul.c: Remove dead SMP-related code target/arm: Add missing break statement for Hypervisor Trap Exception Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-22target/arm: Limit ID register assertions to TCGPeter Maydell
In arm_cpu_realizefn() we make several assertions about the values of guest ID registers: * if the CPU provides AArch32 v7VE or better it must advertise the ARM_DIV feature * if the CPU provides AArch32 A-profile v6 or better it must advertise the Jazelle feature These are essentially consistency checks that our ID register specifications in cpu.c didn't accidentally miss out a feature, because increasingly the TCG emulation gates features on the values in ID registers rather than using old-style checks of ARM_FEATURE_FOO bits. Unfortunately, these asserts can cause problems if we're running KVM, because in that case we don't control the values of the ID registers -- we read them from the host kernel. In particular, if the host kernel is older than 4.15 then it doesn't expose the ID registers via the KVM_GET_ONE_REG ioctl, and we set up dummy values for some registers and leave the rest at zero. (See the comment in target/arm/kvm64.c kvm_arm_get_host_cpu_features().) This set of dummy values is not sufficient to pass our assertions, and so on those kernels running an AArch32 guest on AArch64 will assert. We could provide a more sophisticated set of dummy ID registers in this case, but that still leaves the possibility of a host CPU which reports bogus ID register values that would cause us to assert. It's more robust to only do these ID register checks if we're using TCG, as that is the only case where this is truly a QEMU code bug. Reported-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190718125928.20147-1-peter.maydell@linaro.org Fixes: https://bugs.launchpad.net/qemu/+bug/1830864 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-22target/arm: Add missing break statement for Hypervisor Trap ExceptionPhilippe Mathieu-Daudé
Reported by GCC9 when building with -Wimplicit-fallthrough=2: target/arm/helper.c: In function ‘arm_cpu_do_interrupt_aarch32_hyp’: target/arm/helper.c:7958:14: error: this statement may fall through [-Werror=implicit-fallthrough=] 7958 | addr = 0x14; | ~~~~~^~~~~~ target/arm/helper.c:7959:5: note: here 7959 | default: | ^~~~~~~ cc1: all warnings being treated as errors Fixes: b9bc21ff9f9 Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reported-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190719111451.12406-1-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-19target/i386: sev: fix failed message typosJiri Slaby
In these multiline messages, there were typos. Fix them -- add a missing space and remove a superfluous apostrophe. Inspired by Tom's patch. Signed-off-by: Jiri Slaby <jslaby@suse.cz> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: qemu-trivial@nongnu.org Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <20190719104118.17735-1-jslaby@suse.cz> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-07-19i386: indicate that 'pconfig' feature was removed intentionallyDenis V. Lunev
pconfig feature was added in 5131dc433df and removed in 712f807e196. This patch mark this feature as known to QEMU and removed by intentinally. This follows the convention of 9ccb9784b57 and f1a23522b03 dealing with 'osxsave' and 'ospke'. Signed-off-by: Denis V. Lunev <den@openvz.org> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Richard Henderson <rth@twiddle.net> CC: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20190719111222.14943-1-den@openvz.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-07-19target/i386: skip KVM_GET/SET_NESTED_STATE if VMX disabled, or for SVMPaolo Bonzini
Do not allocate env->nested_state unless we later need to migrate the nested virtualization state. With this change, nested_state_needed() will return false if the VMX flag is not included in the virtual machine. KVM_GET/SET_NESTED_STATE is also disabled for SVM which is safer (we know that at least the NPT root and paging mode have to be saved/loaded), and thus the corresponding subsection can go away as well. Inspired by a patch from Liran Alon. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-07-19target/i386: kvm: Demand nested migration kernel capabilities only when vCPU ↵Liran Alon
may have enabled VMX Previous to this change, a vCPU exposed with VMX running on a kernel without KVM_CAP_NESTED_STATE or KVM_CAP_EXCEPTION_PAYLOAD resulted in adding a migration blocker. This was because when the code was written it was thought there is no way to reliably know if a vCPU is utilising VMX or not at runtime. However, it turns out that this can be known to some extent: In order for a vCPU to enter VMX operation it must have CR4.VMXE set. Since it was set, CR4.VMXE must remain set as long as the vCPU is in VMX operation. This is because CR4.VMXE is one of the bits set in MSR_IA32_VMX_CR4_FIXED1. There is one exception to the above statement when vCPU enters SMM mode. When a vCPU enters SMM mode, it temporarily exits VMX operation and may also reset CR4.VMXE during execution in SMM mode. When the vCPU exits SMM mode, vCPU state is restored to be in VMX operation and CR4.VMXE is restored to its original state of being set. Therefore, when the vCPU is not in SMM mode, we can infer whether VMX is being used by examining CR4.VMXE. Otherwise, we cannot know for certain but assume the worse that vCPU may utilise VMX. Summaring all the above, a vCPU may have enabled VMX in case CR4.VMXE is set or vCPU is in SMM mode. Therefore, remove migration blocker and check before migration (cpu_pre_save()) if the vCPU may have enabled VMX. If true, only then require relevant kernel capabilities. While at it, demand KVM_CAP_EXCEPTION_PAYLOAD only when the vCPU is in guest-mode and there is a pending/injected exception. Otherwise, this kernel capability is not required for proper migration. Reviewed-by: Joao Martins <joao.m.martins@oracle.com> Signed-off-by: Liran Alon <liran.alon@oracle.com> Reviewed-by: Maran Wilson <maran.wilson@oracle.com> Tested-by: Maran Wilson <maran.wilson@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-07-16Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190716' into stagingPeter Maydell
straighten out some things in the gen15 cpu model # gpg: Signature made Tue 16 Jul 2019 14:50:34 BST # gpg: using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF # gpg: issuer "cohuck@redhat.com" # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown] # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full] # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full] # gpg: aka "Cornelia Huck <cohuck@kernel.org>" [unknown] # gpg: aka "Cornelia Huck <cohuck@redhat.com>" [unknown] # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20190716: s390x/cpumodel: change internal name of vxpdeh to match description s390x/cpumodel: also change name of vxbeh s390x/cpumodel: remove esort from the default model Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-16Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* VFIO bugfix for AMD SEV (Alex) * Kconfig improvements (Julio, Philippe) * MemoryRegion reference counting bugfix (King Wang) * Build system cleanups (Marc-André, myself) * rdmacm-mux off-by-one (Marc-André) * ZBC passthrough fixes (Shinichiro, myself) * WHPX build fix (Stefan) * char-pty fix (Wei Yang) # gpg: Signature made Tue 16 Jul 2019 08:31:27 BST # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: vl: make sure char-pty message displayed by moving setbuf to the beginning create_config: remove $(CONFIG_SOFTMMU) hack Makefile: do not repeat $(CONFIG_SOFTMMU) in hw/Makefile.objs hw/usb/Kconfig: USB_XHCI_NEC requires USB_XHCI hw/usb/Kconfig: Add CONFIG_USB_EHCI_PCI target/i386: sev: Do not unpin ram device memory region checkpatch: detect doubly-encoded UTF-8 hw/lm32/Kconfig: Milkymist One provides a USB 1.1 Controller util: merge main-loop.c and iohandler.c Fix broken build with WHPX enabled memory: unref the memory region in simplify flatview hw/i386: turn off vmport if CONFIG_VMPORT is disabled rdmacm-mux: fix strcpy string warning build-sys: remove slirp cflags from main-loop.o iscsi: base all handling of check condition on scsi_sense_to_errno iscsi: fix busy/timeout/task set full scsi: add guest-recoverable ZBC errors scsi: explicitly list guest-recoverable sense codes scsi-disk: pass sense correctly for guest-recoverable errors Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-16s390x/cpumodel: change internal name of vxpdeh to match descriptionChristian Borntraeger
The internal macro name VECTOR_BCD_ENH does not match the actual description. Fix this. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20190715142304.215018-4-borntraeger@de.ibm.com> [CH: vxp->vxpdeh, as discussed] Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-07-16s390x/cpumodel: also change name of vxbehChristian Borntraeger
David suggested to keep everything in sync as 4.1 is not yet released. This patch fixes the name "vxbeh" into "vxpdeh". To simplify the backports this patch will not change VECTOR_BCD_ENH as this is just an internal name. That will be done by an extra patch that does not need to be backported. Suggested-by: David Hildenbrand <david@redhat.com> Fixes: d05be57ddc2e ("s390: cpumodel: fix description for the new vector facility") Fixes: 54d65de0b525 ("s390x/cpumodel: vector enhancements") Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20190715142304.215018-3-borntraeger@de.ibm.com> [CH: vxp->vxpdeh, as discussed] Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-07-16s390x/cpumodel: remove esort from the default modelChristian Borntraeger
esort might not be available on all models. Fixes: caef62430fed6e73 ("s390x/cpumodel: add gen15 defintions") Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20190715142304.215018-2-borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-07-15target/mips: Add missing 'break' for certain cases of MTTR handlingAleksandar Markovic
This was found by GCC 8.3 static analysis. Fixes: ead9360e2fb Reported-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1563220847-14630-5-git-send-email-aleksandar.markovic@rt-rk.com>
2019-07-15target/mips: Add missing 'break' for certain cases of MFTR handlingAleksandar Markovic
This was found by GCC 8.3 static analysis. Fixes: ead9360e2fb Reported-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1563220847-14630-4-git-send-email-aleksandar.markovic@rt-rk.com>
2019-07-15target/mips: Add missing 'break' for a case of MTHC0 handlingAleksandar Markovic
This was found by GCC 8.3 static analysis. Fixes: 5fb2dcd1792 Reported-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1563220847-14630-3-git-send-email-aleksandar.markovic@rt-rk.com>
2019-07-15target/i386: sev: Do not unpin ram device memory regionAlex Williamson
The commit referenced below skipped pinning ram device memory when ram blocks are added, we need to do the same when they're removed. Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Fixes: cedc0ad539af ("target/i386: sev: Do not pin the ram device memory region") Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Message-Id: <156320087103.2556.10983987500488190423.stgit@gimli.home> Reviewed-by: Singh, Brijesh <brijesh.singh@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-07-15target/arm: NS BusFault on vector table fetch escalates to NS HardFaultPeter Maydell
In the M-profile architecture, when we do a vector table fetch and it fails, we need to report a HardFault. Whether this is a Secure HF or a NonSecure HF depends on several things. If AIRCR.BFHFNMINS is 0 then HF is always Secure, because there is no NonSecure HardFault. Otherwise, the answer depends on whether the 'underlying exception' (MemManage, BusFault, SecureFault) targets Secure or NonSecure. (In the pseudocode, this is handled in the Vector() function: the final exc.isSecure is calculated by looking at the exc.isSecure from the exception returned from the memory access, not the isSecure input argument.) We weren't doing this correctly, because we were looking at the target security domain of the exception we were trying to load the vector table entry for. This produces errors of two kinds: * a load from the NS vector table which hits the "NS access to S memory" SecureFault should end up as a Secure HardFault, but we were raising an NS HardFault * a load from the S vector table which causes a BusFault should raise an NS HardFault if BFHFNMINS == 1 (because in that case all BusFaults are NonSecure), but we were raising a Secure HardFault Correct the logic. We also fix a comment error where we claimed that we might be escalating MemManage to HardFault, and forgot about SecureFault. (Vector loads can never hit MPU access faults, because they're always aligned and always use the default address map.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190705094823.28905-1-peter.maydell@linaro.org
2019-07-15target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026Peter Maydell
The ARMv5 architecture didn't specify detailed per-feature ID registers. Now that we're using the MVFR0 register fields to gate the existence of VFP instructions, we need to set up the correct values in the cpu->isar structure so that we still provide an FPU to the guest. This fixes a regression in the arm926 and arm1026 CPUs, which are the only ones that both have VFP and are ARMv5 or earlier. This regression was introduced by the VFP refactoring, and more specifically by commits 1120827fa182f0e76 and 266bd25c485597c, which accidentally disabled VFP short-vector support and double-precision support on these CPUs. Fixes: 1120827fa182f0e Fixes: 266bd25c485597c Fixes: https://bugs.launchpad.net/qemu/+bug/1836192 Reported-by: Christophe Lyon <christophe.lyon@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Christophe Lyon <christophe.lyon@linaro.org> Message-id: 20190711131241.22231-1-peter.maydell@linaro.org
2019-07-15target/arm: report ARMv8-A FP support for AArch32 -cpu maxAlex Bennée
When we converted to using feature bits in 602f6e42cfbf we missed out the fact (dp && arm_dc_feature(s, ARM_FEATURE_V8)) was supported for -cpu max configurations. This caused a regression in the GCC test suite. Fix this by setting the appropriate bits in mvfr1.FPHP to report ARMv8-A with FP support (but not ARMv8.2-FP16). Fixes: https://bugs.launchpad.net/qemu/+bug/1836078 Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190711103737.10017-1-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-15Fix broken build with WHPX enabledStefan Weil
Signed-off-by: Stefan Weil <sw@weilnetz.de> Message-Id: <20190712132611.20411-1-sw@weilnetz.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-07-14tcg: Introduce set/clear_helper_retaddrRichard Henderson
At present we have a potential error in that helper_retaddr contains data for handle_cpu_signal, but we have not ensured that those stores will be scheduled properly before the operation that may fault. It might be that these races are not in practice observable, due to our use of -fno-strict-aliasing, but better safe than sorry. Adjust all of the setters of helper_retaddr. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-07-09Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190709' into stagingPeter Maydell
Fixes in cpu models, tcg, and vfio-ccw. # gpg: Signature made Tue 09 Jul 2019 13:20:52 BST # gpg: using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF # gpg: issuer "cohuck@redhat.com" # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown] # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full] # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full] # gpg: aka "Cornelia Huck <cohuck@kernel.org>" [unknown] # gpg: aka "Cornelia Huck <cohuck@redhat.com>" [unknown] # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20190709: s390x/tcg: move fallthrough annotation s390: cpumodel: fix description for the new vector facility s390x/cpumodel: Set up CPU model for AQIC interception vfio-ccw: Test vfio_set_irq_signaling() return value Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-09s390x/tcg: move fallthrough annotationCornelia Huck
...so that the compiler properly recognizes it. Reported-by: Stefan Weil <sw@weilnetz.de> Fixes: f180da83c039 ("s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO") Message-Id: <20190708125433.16927-3-cohuck@redhat.com> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-07-09s390: cpumodel: fix description for the new vector facilityChristian Borntraeger
The new facility is called "Vector-Packed-Decimal-Enhancement Facility" and not "Vector BCD enhancements facility 1". As the shortname might have already found its way into some backports, let's keep vxbeh. Fixes: 54d65de0b525 ("s390x/cpumodel: vector enhancements") Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20190708150931.93448-1-borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-07-08target/arm/vfp_helper: Call set_fpscr_to_host before updating to FPSCRPhilippe Mathieu-Daudé
In commit e9d652824b0 we extracted the vfp_set_fpscr_to_host() function but failed at calling it in the correct place, we call it after xregs[ARM_VFP_FPSCR] is modified. Fix by calling this function before we update FPSCR. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190705124318.1075-1-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-08target/arm: Fix sve_zcr_len_for_elRichard Henderson
Off by one error in the EL2 and EL3 tests. Remove the test against EL3 entirely, since it must always be true. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190702104732.31154-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-08s390x/cpumodel: Set up CPU model for AQIC interceptionPierre Morel
Let's add support for the AP-Queue interruption facility to the CPU model. The S390_FEAT_AP_QUEUE_INTERRUPT_CONTROL, CPU facility indicates whether the PQAP instruction with the AQIC command is available to the guest. This feature will be enabled only if the AP instructions are available on the linux host and AQIC facility is installed on the host. This feature must be turned on from userspace to intercept AP instructions on the KVM guest. The QEMU command line to turn this feature on looks something like this: qemu-system-s390x ... -cpu xxx,apqi=on ... or ... -cpu host Right now AP pass-through devices do not support migration, which means that we do not have to take care of migrating the interrupt data: virsh migrate apguest --live qemu+ssh://root@target.lan/system error: Requested operation is not valid: domain has assigned non-USB host devices Signed-off-by: Pierre Morel <pmorel@linux.ibm.com> Reviewed-by: Tony Krowiak <akrowiak@linux.ibm.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Halil Pasic <pasic@linux.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> [rebase to newest qemu and fixup description] Message-Id: <20190705153249.12525-1-borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-07-08Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
Bugfixes. # gpg: Signature made Fri 05 Jul 2019 21:21:52 BST # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: ioapic: use irq number instead of vector in ioapic_eoi_broadcast hw/i386: Fix linker error when ISAPC is disabled Makefile: generate header file with the list of devices enabled target/i386: kvm: Fix when nested state is needed for migration minikconf: do not include variables from MINIKCONF_ARGS in config-all-devices.mak target/i386: fix feature check in hyperv-stub.c ioapic: clear irq_eoi when updating the ioapic redirect table entry intel_iommu: Fix unexpected unmaps during global unmap intel_iommu: Fix incorrect "end" for vtd_address_space_unmap i386/kvm: Fix build with -m32 checkpatch: do not warn for multiline parenthesized returned value pc: fix possible NULL pointer dereference in pc_machine_get_device_memory_region_size() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-05target/i386: kvm: Fix when nested state is needed for migrationLiran Alon
When vCPU is in VMX operation and enters SMM mode, it temporarily exits VMX operation but KVM maintained nested-state still stores the VMXON region physical address, i.e. even when the vCPU is in SMM mode then (nested_state->hdr.vmx.vmxon_pa != -1ull). Therefore, there is no need to explicitly check for KVM_STATE_NESTED_SMM_VMXON to determine if it is necessary to save nested-state as part of migration stream. Reviewed-by: Karl Heubaum <karl.heubaum@oracle.com> Signed-off-by: Liran Alon <liran.alon@oracle.com> Message-Id: <20190624230514.53326-1-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-07-05target/i386: fix feature check in hyperv-stub.cAlex Bennée
Commit 2d384d7c8 broken the build when built with: configure --without-default-devices --disable-user The reason was the conversion of cpu->hyperv_synic to cpu->hyperv_synic_kvm_only although the rest of the patch introduces a feature checking mechanism. So I've fixed the KVM_EXIT_HYPERV_SYNIC in hyperv-stub to do the same feature check as in the real hyperv.c Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Vitaly Kuznetsov <vkuznets@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Roman Kagan <rkagan@virtuozzo.com> Message-Id: <20190624123835.28869-1-alex.bennee@linaro.org> Reviewed-by: Vitaly Kuznetsov <vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-07-05i386/kvm: Fix build with -m32Max Reitz
find_next_bit() takes a pointer of type "const unsigned long *", but the first argument passed here is a "uint64_t *". These types are incompatible when compiling qemu with -m32. Just use ctz64() instead. Fixes: c686193072a47032d83cb4e131dc49ae30f9e5d Signed-off-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20190624193913.28343-1-mreitz@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-07-05i386: Add Cascadelake-Server-v2 CPU modelEduardo Habkost
Add new version of Cascadelake-Server CPU model, setting stepping=5 and enabling the IA32_ARCH_CAPABILITIES MSR with some flags. The new feature will introduce a new host software requirement, breaking our CPU model runnability promises. This means we can't enable the new CPU model version by default in QEMU 4.1, because management software isn't ready yet to resolve CPU model aliases. This is why "pc-*-4.1" will keep returning Cascadelake-Server-v1 if "-cpu Cascadelake-Server" is specified. Includes a test case to ensure the right combinations of machine-type + CPU model + command-line feature flags will work as expected. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20190628002844.24894-10-ehabkost@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20190703221723.8161-1-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-07-05i386: Make unversioned CPU models be aliasesEduardo Habkost
This will make unversioned CPU models behavior depend on the machine type: * "pc-*-4.0" and older will not report them as aliases. This is done to keep compatibility with older QEMU versions after management software starts translating aliases. * "pc-*-4.1" will translate unversioned CPU models to -v1. This is done to keep compatibility with existing management software, that still relies on CPU model runnability promises. * "none" will translate unversioned CPU models to their latest version. This is planned become the default in future machine types (probably in pc-*-4.3). Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20190628002844.24894-8-ehabkost@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-07-05i386: Replace -noTSX, -IBRS, -IBPB CPU models with aliasesEduardo Habkost
The old CPU models will be just aliases for specific versions of the original CPU models. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20190628002844.24894-7-ehabkost@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-07-05i386: Define -IBRS, -noTSX, -IBRS versions of CPU modelsEduardo Habkost
Add versions of CPU models that are equivalent to their -IBRS, -noTSX and -IBRS variants. The separate variants will eventually be removed and become aliases for these CPU versions. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20190628002844.24894-6-ehabkost@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-07-05i386: Register versioned CPU modelsEduardo Habkost
Add support for registration of multiple versions of CPU models. The existing CPU models will be registered with a "-v1" suffix. The -noTSX, -IBRS, and -IBPB CPU model variants will become versions of the original models in a separate patch, so make sure we register no versions for them. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20190628002844.24894-5-ehabkost@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-07-05i386: Get model-id from CPU object on "-cpu help"Eduardo Habkost
When introducing versioned CPU models, the string at X86CPUDefinition::model_id might not be the model-id we'll really use. Instantiate a CPU object and check the model-id property on "-cpu help" Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20190628002844.24894-4-ehabkost@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-07-05i386: Add x-force-features option for testingEduardo Habkost
Add a new option that can be used to disable feature flag filtering. This will allow CPU model compatibility test cases to work without host hardware dependencies. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20190628002844.24894-3-ehabkost@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-07-05i386: Introduce SnowRidge CPU modelPaul Lai
SnowRidge CPU supports Accelerator Infrastrcture Architecture (MOVDIRI, MOVDIR64B), CLDEMOTE and SPLIT_LOCK_DISABLE. MOVDIRI, MOVDIR64B, and CLDEMOTE are found via CPUID. The availability of SPLIT_LOCK_DISABLE is check via msr access References can be found in either: https://software.intel.com/en-us/articles/intel-sdm https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-and-future-features-programming-reference Signed-off-by: Paul Lai <paul.c.lai@intel.com> Tested-by: Tao3 Xu <tao3.xu@intel.com> Message-Id: <20190626162129.25345-1-paul.c.lai@intel.com> [ehabkost: squashed SPLIT_LOCK_DETECT patch] Message-Id: <20190626163232.25711-1-paul.c.lai@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-07-05target/i386: Add CPUID.1F generation support for multi-dies PCMachineLike Xu
The CPUID.1F as Intel V2 Extended Topology Enumeration Leaf would be exposed if guests want to emulate multiple software-visible die within each package. Per Intel's SDM, the 0x1f is a superset of 0xb, thus they can be generated by almost same code as 0xb except die_offset setting. If the number of dies per package is greater than 1, the cpuid_min_level would be adjusted to 0x1f regardless of whether the host supports CPUID.1F. Likewise, the CPUID.1F wouldn't be exposed if env->nr_dies < 2. Suggested-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Like Xu <like.xu@linux.intel.com> Message-Id: <20190620054525.37188-2-like.xu@linux.intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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