slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2024-10-31	target/i386: use compiler builtin to compute PF	Paolo Bonzini
2024-10-31	target/i386: make flag variables unsigned	Paolo Bonzini
2024-10-31	target/i386: add a note about gen_jcc1	Paolo Bonzini
2024-10-31	target/i386: add a few more trivial CCPrepare cases	Paolo Bonzini
2024-10-31	target/i386: optimize TEST+Jxx sequences	Paolo Bonzini
2024-10-31	target/i386: optimize computation of ZF from CC_OP_DYNAMIC	Paolo Bonzini
2024-10-31	target/i386: Wrap cc_op_live with a validity check	Richard Henderson
2024-10-31	target/i386: Introduce cc_op_size	Richard Henderson
2024-10-31	target/i386: Rearrange CCOp	Richard Henderson
2024-10-31	target/i386: remove CC_OP_CLR	Paolo Bonzini
2024-10-31	target/i386: Tidy cc_op_str usage	Richard Henderson
2024-10-31	target/i386: use tcg_gen_ext_tl when applicable	Paolo Bonzini
2024-10-31	target/i386/hvf: fix handling of XSAVE-related CPUID bits	Paolo Bonzini
2024-10-31	target/i386: Expose new feature bits in CPUID 8000_0021_EAX/EBX	Babu Moger
2024-10-31	target/i386: Expose bits related to SRSO vulnerability	Babu Moger
2024-10-31	target/i386: Add PerfMonV2 feature bit	Sandipan Das
2024-10-31	target/i386: Fix minor typo in NO_NESTED_DATA_BP feature bit	Babu Moger
2024-10-31	i386/cpu: Drop the check of phys_bits in host_cpu_realizefn()	Xiaoyao Li
2024-10-31	Merge tag 'pull-riscv-to-apply-20241031-1' of https://github.com/alistair23/q...	Peter Maydell
2024-10-31	target/riscv: Fix vcompress with rvv_ta_all_1s	Anton Blanchard
2024-10-31	target/riscv/kvm: clarify how 'riscv-aia' default works	Daniel Henrique Barboza
2024-10-31	target/riscv/kvm: set 'aia_mode' to default in error path	Daniel Henrique Barboza
2024-10-31	target/riscv: Expose zicfiss extension as a cpu property	Deepak Gupta
2024-10-30	target/i386: fix CPUID check for LFENCE and SFENCE	Paolo Bonzini
2024-10-30	target/riscv: compressed encodings for sspush and sspopchk	Deepak Gupta
2024-10-30	target/riscv: implement zicfiss instructions	Deepak Gupta
2024-10-30	target/riscv: update `decode_save_opc` to store extra word2	Deepak Gupta
2024-10-30	target/riscv: AMO operations always raise store/AMO fault	Deepak Gupta
2024-10-30	target/riscv: mmu changes for zicfiss shadow stack protection	Deepak Gupta
2024-10-30	target/riscv: tb flag for shadow stack instructions	Deepak Gupta
2024-10-30	target/riscv: introduce ssp and enabling controls for zicfiss	Deepak Gupta
2024-10-30	target/riscv: Add zicfiss extension	Deepak Gupta
2024-10-30	target/riscv: Expose zicfilp extension as a cpu property	Deepak Gupta
2024-10-30	target/riscv: zicfilp `lpad` impl and branch tracking	Deepak Gupta
2024-10-30	target/riscv: tracking indirect branches (fcfi) for zicfilp	Deepak Gupta
2024-10-30	target/riscv: additional code information for sw check	Deepak Gupta
2024-10-30	target/riscv: save and restore elp state on priv transitions	Deepak Gupta
2024-10-30	target/riscv: Introduce elp state and enabling controls for zicfilp	Deepak Gupta
2024-10-30	target/riscv: Add zicfilp extension	Deepak Gupta
2024-10-30	target/riscv: expose *envcfg csr and priv to qemu-user as well	Deepak Gupta
2024-10-30	target/riscv: Set vtype.vill on CPU reset	Rob Bradford
2024-10-30	target/riscv: Add max32 CPU for RV64 QEMU	LIU Zhiwei
2024-10-30	target/riscv: Enable RV32 CPU support in RV64 QEMU	TANG Tiancheng
2024-10-30	target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU	TANG Tiancheng
2024-10-30	target/riscv: Detect sxl to set bit width for RV32 in RV64	TANG Tiancheng
2024-10-30	target/riscv: Correct SXL return value for RV32 in RV64 QEMU	TANG Tiancheng
2024-10-30	target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32	TANG Tiancheng
2024-10-30	target/riscv/csr.c: Fix an access to VXSAT	Evgenii Prokopiev
2024-10-29	target/arm: kvm: require KVM_CAP_DEVICE_CTRL	Paolo Bonzini
2024-10-29	target/arm: Fix arithmetic underflow in SETM instruction	Ido Plat