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2023-11-07target/riscv: Move vector crypto extensions to riscv_cpu_extensionsMax Chou
2023-11-07target/riscv: Expose Zvks[c|g] extnesion propertiesMax Chou
2023-11-07target/riscv: Add cfg properties for Zvks[c|g] extensionsMax Chou
2023-11-07target/riscv: Expose Zvkn[c|g] extnesion propertiesMax Chou
2023-11-07target/riscv: Add cfg properties for Zvkn[c|g] extensionsMax Chou
2023-11-07target/riscv: Expose Zvkb extension propertyMax Chou
2023-11-07target/riscv: Replace Zvbb checking by ZvkbMax Chou
2023-11-07target/riscv: Add cfg property for Zvkb extensionMax Chou
2023-11-07target/riscv: Expose Zvkt extension propertyMax Chou
2023-11-07target/riscv: Add cfg property for Zvkt extensionMax Chou
2023-11-07target/riscv: correct csr_ops[CSR_MSECCFG]Heinrich Schuchardt
2023-11-07target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapotDaniel Henrique Barboza
2023-11-07target/riscv/kvm: add zihpm regDaniel Henrique Barboza
2023-11-07target/riscv: add zihpm extension flag for TCGDaniel Henrique Barboza
2023-11-07target/riscv/kvm: add zicntr regDaniel Henrique Barboza
2023-11-07target/riscv: add zicntr extension flag for TCGDaniel Henrique Barboza
2023-11-07target/riscv: pmp: Ignore writes when RW=01Mayuresh Chitale
2023-11-07target/riscv: pmp: Clear pmp/smepmp bits on resetMayuresh Chitale
2023-11-07Add epmp to extensions list and rename it to smepmpHimanshu Chauhan
2023-11-07target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansionDaniel Henrique Barboza
2023-11-07target/riscv: add riscv_cpu_accelerator_compatible()Daniel Henrique Barboza
2023-11-07target/riscv: handle custom props in qmp_query_cpu_model_expansionDaniel Henrique Barboza
2023-11-07target/riscv/tcg: add tcg_cpu_finalize_features()Daniel Henrique Barboza
2023-11-07qapi,risc-v: add query-cpu-model-expansionDaniel Henrique Barboza
2023-11-07target/riscv/kvm/kvm-cpu.c: add missing property getters()Daniel Henrique Barboza
2023-11-07target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal
2023-11-07target/riscv: Add M-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal
2023-11-07target/riscv: Split interrupt logic from riscv_cpu_update_mip.Rajnesh Kanwal
2023-11-07target/riscv: Set VS* bits to one in mideleg when H-Ext is enabledRajnesh Kanwal
2023-11-07target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.Rajnesh Kanwal
2023-11-07target/riscv: Without H-mode mask all HS mode inturrupts in mie.Rajnesh Kanwal
2023-11-07target/riscv: rename ext_icboz to ext_zicbozDaniel Henrique Barboza
2023-11-07target/riscv: rename ext_icbom to ext_zicbomDaniel Henrique Barboza
2023-11-07target/riscv: rename ext_icsr to ext_zicsrDaniel Henrique Barboza
2023-11-07target/riscv: rename ext_ifencei to ext_zifenceiDaniel Henrique Barboza
2023-11-06Merge tag 'pull-sp-20231105' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi
2023-11-05target/sparc: Check for invalid cond in gen_compare_regRichard Henderson
2023-11-05target/sparc: Implement UDIV inlineRichard Henderson
2023-11-05target/sparc: Implement UDIVX and SDIVX inlineRichard Henderson
2023-11-05target/sparc: Discard cpu_cond at the end of each insnRichard Henderson
2023-11-05target/sparc: Record entire jump condition in DisasContextRichard Henderson
2023-11-05target/sparc: Merge gen_op_next_insn into only callerRichard Henderson
2023-11-05target/sparc: Pass displacement to advance_jump_condRichard Henderson
2023-11-05target/sparc: Merge advance_jump_uncond_{never,always} into advance_jump_condRichard Henderson
2023-11-05target/sparc: Merge gen_branch2 into advance_pcRichard Henderson
2023-11-05target/sparc: Do flush_cond in advance_jump_condRichard Henderson
2023-11-05target/sparc: Always copy conditions into a new temporaryRichard Henderson
2023-11-05target/sparc: Change DisasCompare.c2 to intRichard Henderson
2023-11-05target/sparc: Remove DisasCompare.is_boolRichard Henderson
2023-11-05target/sparc: Remove CC_OP leftoversRichard Henderson