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2024-05-29target/s390x: Split per_breaking_event from per_branch_*Richard Henderson
The breaking-event-address register is updated regardless of PER being enabled. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240502054417.234340-9-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29target/s390x: Simplify help_branchRichard Henderson
Always use a tcg branch, instead of movcond. The movcond was not a bad idea before PER was added, but since then we have either 2 or 3 actions to perform on each leg of the branch, and multiple movcond is inefficient. Reorder the taken branch to be fallthrough of the tcg branch. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240502054417.234340-8-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29target/s390x: Introduce help_goto_indirectRichard Henderson
Add a small helper to handle unconditional indirect jumps. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240502054417.234340-7-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29target/s390x: Disable conditional branch-to-next for PERRichard Henderson
For PER, we require a conditional call to helper_per_branch for the conditional branch. Fold the remaining optimization into a call to helper_goto_direct, which will take care of the remaining gbea adjustment. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240502054417.234340-6-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29target/s390x: Record separate PER bits in TB flagsRichard Henderson
Record successful-branching, instruction-fetching, and store-using-real-address. The other PER bits are not used during translation. Having checked these at translation time, we can remove runtime tests from the helpers. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-ID: <20240502054417.234340-5-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29target/s390x: Update CR9 bitsRichard Henderson
Update from the PoO 14th edition. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-ID: <20240502054417.234340-4-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29target/s390x: Move cpu_get_tb_cpu_state out of lineRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-ID: <20240502054417.234340-3-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29target/s390x: Do not use unwind for per_check_exceptionRichard Henderson
Using exception unwind via tcg_s390_program_interrupt, we discard the current value of psw.addr, which discards the result of a branch. Pass in the address of the next instruction, which may not be sequential. Pass in ilen, which we would have gotten from unwind and is passed to the exception handler. Sync cc_op before the call, which we would have gotten from unwind. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-ID: <20240502054417.234340-2-richard.henderson@linaro.org> [thuth: Silence checkpatch.pl errors] Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-28target/arm: Convert disas_simd_3same_logic to decodetreeRichard Henderson
This includes AND, ORR, EOR, BIC, ORN, BSF, BIT, BIF. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-37-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Convert FMLAL, FMLSL to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-36-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Use gvec for neon pmax, pminRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-35-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Convert SMAXP, SMINP, UMAXP, UMINP to decodetreeRichard Henderson
These are the last instructions within handle_simd_3same_pair so remove it. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-34-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Use gvec for neon paddRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-33-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Convert ADDP to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-32-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Use gvec for neon faddp, fmaxp, fminpRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-31-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Convert FMAXP, FMINP, FMAXNMP, FMINNMP to decodetreeRichard Henderson
These are the last instructions within disas_simd_three_reg_same_fp16, so remove it. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-30-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Convert FADDP to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-29-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Convert FRECPS, FRSQRTS to decodetreeRichard Henderson
These are the last instructions within handle_3same_float and disas_simd_scalar_three_reg_same_fp16 so remove them. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-28-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Convert FABD to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-27-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Convert FCMEQ, FCMGE, FCMGT, FACGE, FACGT to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-26-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Convert FMLA, FMLS to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Convert FNMUL to decodetreeRichard Henderson
This is the last instruction within disas_fp_2src, so remove that and its subroutines. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Expand vfp neg and abs inlineRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Introduce vfp_load_reg16Richard Henderson
Load and zero-extend float16 into a TCGv_i32 before all scalar operations. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240524232121.284515-22-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Convert FMAX, FMIN, FMAXNM, FMINNM to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Convert FADD, FSUB, FDIV, FMUL to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Convert FMULX to decodetreeRichard Henderson
Convert all forms (scalar, vector, scalar indexed, vector indexed), which allows us to remove switch table entries elsewhere. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Convert Advanced SIMD copy to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Convert XAR to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Convert Cryptographic 3-register, imm2 to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Convert Cryptographic 4-register to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Convert Cryptographic 2-register SHA512 to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Convert Cryptographic 3-register SHA512 to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Convert Cryptographic 2-register SHA to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Convert Cryptographic 3-register SHA to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Convert Cryptographic AES to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Split out gengvec64.cRichard Henderson
Split some routines out of translate-a64.c and translate-sve.c that are used by both. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Split out gengvec.cRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Verify sz=0 for Advanced SIMD scalar pairwise (fp16)Richard Henderson
All of these insns have "if sz == '1' then UNDEFINED" in their pseudocode. Fixes a RISU miscompare for invalid insn 0x5ef0c87a. Fixes: 5c36d89567c ("arm/translate-a64: add all FP16 ops in simd_scalar_pairwise") Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240524232121.284515-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Fix decode of FMOV (hp) vs MOVIRichard Henderson
The decode of FMOV (vector, immediate, half-precision) vs invalid cases of MOVI are incorrect. Fixes RISU mismatch for invalid insn 0x2f01fd31. Fixes: 70b4e6a4457 ("arm/translate-a64: add FP16 FMOV to simd_mod_imm") Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240524232121.284515-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Zero-extend writeback for fp16 FCVTZS (scalar, integer)Richard Henderson
Fixes RISU mismatch for "fcvtzs h31, h0, #14". Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240524232121.284515-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28target/arm: Use PLD, PLDW, PLI not NOP for t32Richard Henderson
This fixes a bug in that neither PLI nor PLDW are present in ARMv6T2, but are introduced with ARMv7 and ARMv7MP respectively. For clarity, do not use NOP for PLD. Note that there is no PLDW (literal). Architecturally in the T1 encoding of "PLD (literal)" bit 5 is "(0)", which means that it should be zero and if it is not then the behaviour is CONSTRAINED UNPREDICTABLE (might UNDEF, NOP, or ignore the value of the bit). In our implementation we have patterns for both: + PLD 1111 1000 -001 1111 1111 ------------ # (literal) + PLD 1111 1000 -011 1111 1111 ------------ # (literal) and so we effectively ignore the value of bit 5. (This is a permitted option for this CONSTRAINED UNPREDICTABLE.) This isn't a behaviour change in this commit, since we previously had NOP lines for both those patterns. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240524232121.284515-3-richard.henderson@linaro.org [PMM: adjusted commit message to note that PLD (lit) T1 bit 5 being 1 is an UNPREDICTABLE case.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28hvf: arm: Fix encodings for ID_AA64PFR1_EL1 and debug System registersZenghui Yu
We wrongly encoded ID_AA64PFR1_EL1 using {3,0,0,4,2} in hvf_sreg_match[] so we fail to get the expected ARMCPRegInfo from cp_regs hash table with the wrong key. Fix it with the correct encoding {3,0,0,4,1}. With that fixed, the Linux guest can properly detect FEAT_SSBS2 on my M1 HW. All DBG{B,W}{V,C}R_EL1 registers are also wrongly encoded with op0 == 14. It happens to work because HVF_SYSREG(CRn, CRm, 14, op1, op2) equals to HVF_SYSREG(CRn, CRm, 2, op1, op2), by definition. But we shouldn't rely on it. Cc: qemu-stable@nongnu.org Fixes: a1477da3ddeb ("hvf: Add Apple Silicon support") Signed-off-by: Zenghui Yu <zenghui.yu@linux.dev> Reviewed-by: Alexander Graf <agraf@csgraf.de> Message-id: 20240503153453.54389-1-zenghui.yu@linux.dev Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-26Merge tag 'pull-lu-20240526' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson
target/i386: Introduce X86Access and use for xsave and friends linux-user/i386: Fix allocation and alignment of fp state in signal frame # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmZT2GwdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV87pQf9F/cmrKQG1mVWKmJd # MI7l63lbxejdgAADv1nmro+oapCsJSaQeUSrYp904ydqJjVfBJkaoXfknGsvxrNA # oW7nEuYt0sBKdaBUKhYpMOJ3ivfw7lVVMJmjNv9ngZRhW+WOoJrBHoleUkVLiM7D # rxkMLL+LQ7BR9i0Lv1unorOkqUPGNOnEd45qRn6k1g/Qnqi8SNMzxFwO8+232u8m # EG9un/oh4mKPyb5vSg3Y4JLg+yDKCRScBqBU1wcKFe1u+umBkv2BNcU+k62AJh1q # bv8i1n+X/dFAd1aj0NEupi04EOZIof5m3T4YIWg7M4I94NiFWNZ18vgskkmiO+Mo # 0KPd/A== # =sYrE # -----END PGP SIGNATURE----- # gpg: Signature made Sun 26 May 2024 05:48:44 PM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-lu-20240526' of https://gitlab.com/rth7680/qemu: (28 commits) target/i386: Pass host pointer and size to cpu_x86_{xsave,xrstor} target/i386: Pass host pointer and size to cpu_x86_{fxsave,fxrstor} target/i386: Pass host pointer and size to cpu_x86_{fsave,frstor} target/i386: Convert do_xrstor to X86Access target/i386: Convert do_xsave to X86Access linux-user/i386: Honor xfeatures in xrstor_sigcontext linux-user/i386: Fix allocation and alignment of fp state linux-user/i386: Return boolean success from xrstor_sigcontext linux-user/i386: Return boolean success from restore_sigcontext linux-user/i386: Fix -mregparm=3 for signal delivery linux-user/i386: Split out struct target_fregs_state linux-user/i386: Replace target_fpstate_fxsave with X86LegacyXSaveArea linux-user/i386: Remove xfeatures from target_fpstate_fxsave linux-user/i386: Drop xfeatures_size from sigcontext arithmetic target/i386: Add {hw,sw}_reserved to X86LegacyXSaveArea target/i386: Add rbfm argument to cpu_x86_{xsave,xrstor} target/i386: Split out do_xsave_chk target/i386: Convert do_xrstor_* to X86Access target/i386: Convert do_xsave_* to X86Access tagret/i386: Convert do_fxsave, do_fxrstor to X86Access ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-26target/i386: Pass host pointer and size to cpu_x86_{xsave,xrstor}Richard Henderson
We have already validated the memory region in the course of validating the signal frame. No need to do it again within the helper function. In addition, return failure when the header contains invalid xstate_bv. The kernel handles this via exception handling within XSTATE_OP within xrstor_from_user_sigframe. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-26target/i386: Pass host pointer and size to cpu_x86_{fxsave,fxrstor}Richard Henderson
We have already validated the memory region in the course of validating the signal frame. No need to do it again within the helper function. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-26target/i386: Pass host pointer and size to cpu_x86_{fsave,frstor}Richard Henderson
We have already validated the memory region in the course of validating the signal frame. No need to do it again within the helper function. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-26target/i386: Convert do_xrstor to X86AccessRichard Henderson
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-26target/i386: Convert do_xsave to X86AccessRichard Henderson
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-26target/i386: Add {hw,sw}_reserved to X86LegacyXSaveAreaRichard Henderson
This completes the 512 byte structure, allowing the union to be removed. Assert that the structure layout is as expected. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>