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2024-07-01target/arm: Convert BFDOT to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240625183536.1672454-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-07-01target/arm: Convert SUDOT, USDOT to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240625183536.1672454-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-07-01target/arm: Convert SDOT, UDOT to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240625183536.1672454-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-07-01target/arm: Convert SQRDMLAH, SQRDMLSH to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240625183536.1672454-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-07-01target/arm: Fix FJCVTZS vs flush-to-zeroRichard Henderson
Input denormals cause the Javascript inexact bit (output to Z) to be set. Cc: qemu-stable@nongnu.org Fixes: 6c1f6f2733a ("target/arm: Implement ARMv8.3-JSConv") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2375 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240625183536.1672454-4-richard.henderson@linaro.org [PMM: fixed hardcoded tab in test case] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-07-01target/arm: Fix SQDMULH (by element) with Q=0Richard Henderson
The inner loop, bounded by eltspersegment, must not be larger than the outer loop, bounded by elements. Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240625183536.1672454-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-07-01target/arm: Fix VCMLA Dd, Dn, Dm[idx]Richard Henderson
The inner loop, bounded by eltspersegment, must not be larger than the outer loop, bounded by elements. Cc: qemu-stable@nongnu.org Fixes: 18fc2405781 ("target/arm: Implement SVE fp complex multiply add (indexed)") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2376 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240625183536.1672454-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-06-30target/i386: Advertise MWAIT iff host supportsZide Chen
host_cpu_realizefn() sets CPUID_EXT_MONITOR without consulting host/KVM capabilities. This may cause problems: - If MWAIT/MONITOR is not available on the host, advertising this feature to the guest and executing MWAIT/MONITOR from the guest triggers #UD and the guest doesn't boot. This is because typically #UD takes priority over VM-Exit interception checks and KVM doesn't emulate MONITOR/MWAIT on #UD. - If KVM doesn't support KVM_X86_DISABLE_EXITS_MWAIT, MWAIT/MONITOR from the guest are intercepted by KVM, which is not what cpu-pm=on intends to do. In these cases, MWAIT/MONITOR should not be exposed to the guest. The logic in kvm_arch_get_supported_cpuid() to handle CPUID_EXT_MONITOR is correct and sufficient, and we can't set CPUID_EXT_MONITOR after x86_cpu_filter_features(). This was not an issue before commit 662175b91ff ("i386: reorder call to cpu_exec_realizefn") because the feature added in the accel-specific realizefn could be checked against host availability and filtered out. Additionally, it seems not a good idea to handle guest CPUID leaves in host_cpu_realizefn(), and this patch merges host_cpu_enable_cpu_pm() into kvm_cpu_realizefn(). Fixes: f5cc5a5c1686 ("i386: split cpu accelerators from cpu.c, using AccelCPUClass") Fixes: 662175b91ff2 ("i386: reorder call to cpu_exec_realizefn") Signed-off-by: Zide Chen <zide.chen@intel.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-06-28target/i386/sev: Fix printf formatsRichard Henderson
hwaddr uses HWADDR_PRIx, sizeof yields size_t so uses %zu, and gsize uses G_GSIZE_FORMAT. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20240626194950.1725800-4-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-28target/i386/sev: Use size_t for object sizesRichard Henderson
This code was using both uint32_t and uint64_t for len. Consistently use size_t instead. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20240626194950.1725800-3-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-28target/i386: SEV: store pointer to decoded id_auth in SevSnpGuestPaolo Bonzini
Do not rely on finish->id_auth_uaddr, so that there are no casts from pointer to uint64_t. They break on 32-bit hosts. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-28target/i386: SEV: rename sev_snp_guest->id_authPaolo Bonzini
Free the "id_auth" name for the binary version of the data. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-28target/i386: SEV: store pointer to decoded id_block in SevSnpGuestPaolo Bonzini
Do not rely on finish->id_block_uaddr, so that there are no casts from pointer to uint64_t. They break on 32-bit hosts. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-28target/i386: SEV: rename sev_snp_guest->id_blockPaolo Bonzini
Free the "id_block" name for the binary version of the data. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-28target/i386: remove unused enumPaolo Bonzini
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-28target/i386: give CC_OP_POPCNT low bits corresponding to MO_TLPaolo Bonzini
Handle it like the other arithmetic cc_ops. This simplifies a bit the implementation of bit test instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-28target/i386: use cpu_cc_dst for CC_OP_POPCNTPaolo Bonzini
It is the only CCOp, among those that compute ZF from one of the cc_op_* registers, that uses cpu_cc_src. Do not make it the odd one off, instead use cpu_cc_dst like the others. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-28target/i386: fix CC_OP dumpPaolo Bonzini
POPCNT was missing, and the entries were all out of order after ADCX/ADOX/ADCOX were moved close to EFLAGS. Just use designated initializers. Fixes: 4885c3c4953 ("target-i386: Use ctpop helper", 2017-01-10) Fixes: cc155f19717 ("target/i386: rewrite flags writeback for ADCX/ADOX", 2024-06-11) Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-27target/riscv: Apply modularized matching conditions for icount triggerAlvin Chang
We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. We can invoke trigger_common_match() to check the privilege levels of the type 3 triggers. Signed-off-by: Alvin Chang <alvinga@andestech.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240626132247.2761286-4-alvinga@andestech.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-27target/riscv: Apply modularized matching conditions for watchpointAlvin Chang
We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. Remove the related code in riscv_cpu_debug_check_watchpoint() and invoke trigger_common_match() to check the privilege levels of the type 2 and type 6 triggers for the watchpoints. This commit also changes the behavior of looping the triggers. In previous implementation, if we have a type 2 trigger and env->virt_enabled is true, we directly return false to stop the loop. Now we keep looping all the triggers until we find a matched trigger. Only load/store bits and loaded/stored address should be further checked in riscv_cpu_debug_check_watchpoint(). Signed-off-by: Alvin Chang <alvinga@andestech.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240626132247.2761286-3-alvinga@andestech.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-27target/riscv: Add functions for common matching conditions of triggerAlvin Chang
According to RISC-V Debug specification version 0.13 [1] (also applied to version 1.0 [2] but it has not been ratified yet), there are several common matching conditions before firing a trigger, including the enabled privilege levels of the trigger. This commit adds trigger_common_match() to prepare the common matching conditions for the type 2/3/6 triggers. For now, we just implement trigger_priv_match() to check if the enabled privilege levels of the trigger match CPU's current privilege level. Remove the related code in riscv_cpu_debug_check_breakpoint() and invoke trigger_common_match() to check the privilege levels of the type 2 and type 6 triggers for the breakpoints. This commit also changes the behavior of looping the triggers. In previous implementation, if we have a type 2 trigger and env->virt_enabled is true, we directly return false to stop the loop. Now we keep looping all the triggers until we find a matched trigger. Only the execution bit and the executed PC should be futher checked in riscv_cpu_debug_check_breakpoint(). [1]: https://github.com/riscv/riscv-debug-spec/releases/tag/task_group_vote [2]: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc1-asciidoc Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240626132247.2761286-2-alvinga@andestech.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Remove extension auto-update check statementsFrank Chang
Remove the old-fashioned extension auto-update check statements as they are replaced by the extension implied rules. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Tested-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240625114629.27793-7-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Add Zc extension implied ruleFrank Chang
Zc extension has special implied rules that need to be handled separately. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Tested-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240625114629.27793-6-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Add multi extension implied rulesFrank Chang
Add multi extension implied rules to enable the implied extensions of the multi extension recursively. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Tested-by: Max Chou <max.chou@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240625114629.27793-5-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Add MISA extension implied rulesFrank Chang
Add MISA extension implied rules to enable the implied extensions of MISA recursively. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Tested-by: Max Chou <max.chou@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240625114629.27793-4-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Introduce extension implied rule helpersFrank Chang
Introduce helpers to enable the extensions based on the implied rules. The implied extensions are enabled recursively, so we don't have to expand all of them manually. This also eliminates the old-fashioned ordering requirement. For example, Zvksg implies Zvks, Zvks implies Zvksed, etc., removing the need to check the implied rules of Zvksg before Zvks. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Tested-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240625114629.27793-3-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Introduce extension implied rules definitionFrank Chang
RISCVCPUImpliedExtsRule is created to store the implied rules. 'is_misa' flag is used to distinguish whether the rule is derived from the MISA or other extensions. 'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores the offset of the extension defined in RISCVCPUConfig. 'ext' will also serve as the key of the hash tables to look up the rule in the following commit. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Tested-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240625114629.27793-2-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: fix instructions count handling in icount modeClément Léger
When icount is enabled, rather than returning the virtual CPU time, we should return the instruction count itself. Add an instructions bool parameter to get_ticks() to correctly return icount_get_raw() when icount_enabled() == 1 and instruction count is queried. This will modify the existing behavior which was returning an instructions count close to the number of cycles (CPI ~= 1). Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Message-ID: <20240618112649.76683-1-cleger@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Fix froundnx.h nanbox checkBranislav Brzak
helper_froundnx_h function mistakenly uses single percision nanbox check instead of the half percision one. This patch fixes the issue. Signed-off-by: Branislav Brzak <brzakbranislav@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240608214546.226963-1-brzakbranislav@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Support the version for ss1p13Fea.Wang
Add RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liwei1518@gmail.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20240606135454.119186-7-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Reserve exception codes for sw-check and hw-errFea.Wang
Based on the priv-1.13.0, add the exception codes for Software-check and Hardware-error. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606135454.119186-6-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32Fea.Wang
Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH and HEDELEGH for exception codes 32-47 for reserving and exception codes 48-63 for custom use. Add the CSR number though the implementation is just reading zero and writing ignore. Besides, for accessing HEDELEGH, it should be controlled by mstateen0 'P1P13' bit. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606135454.119186-5-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Add 'P1P13' bit in SMSTATEEN0Fea.Wang
Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in mstateen0 that controls access to the hedeleg. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liwei1518@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606135454.119186-4-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Define macros and variables for ss1p13Fea.Wang
Add macros and variables for RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liwei1518@gmail.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606135454.119186-3-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Reuse the conversion function of priv_specJim Shu
Public the conversion function of priv_spec in cpu.h, so that tcg-cpu.c could also use it. Signed-off-by: Jim Shu <jim.shu@sifive.com> Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606135454.119186-2-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv/kvm: handle the exit with debug reasonChao Du
If the breakpoint belongs to the userspace then set the ret value. Signed-off-by: Chao Du <duchao@eswincomputing.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606014501.20763-3-duchao@eswincomputing.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv/kvm: add software breakpoints supportChao Du
This patch implements insert/remove software breakpoint process. For RISC-V, GDB treats single-step similarly to breakpoint: add a breakpoint at the next step address, then continue. So this also works for single-step debugging. Implement kvm_arch_update_guest_debug(): Set the control flag when there are active breakpoints. This will help KVM to know the status in the userspace. Add some stubs which are necessary for building, and will be implemented later. Signed-off-by: Chao Du <duchao@eswincomputing.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606014501.20763-2-duchao@eswincomputing.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: zvbb implies zvkbJerry Zhang Jian
According to RISC-V crypto spec, Zvkb extension is a subset of the Zvbb extension [1]. 1: https://github.com/riscv/riscv-crypto/blob/1769c2609bf4535632e0c0fd715778f212bb272e/doc/vector/riscv-crypto-vector-zvkb.adoc?plain=1#L10 Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240528130349.20193-1-jerry.zhangjian@sifive.com> [ Changes by AF: - Tidy up commit message - Rebase ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Move Guest irqs out of the core local irqs range.Rajnesh Kanwal
Qemu maps IRQs 0:15 for core interrupts and 16 onward for guest interrupts which are later translated to hgiep in `riscv_cpu_set_irq()` function. With virtual IRQ support added, software now can fully use the whole local interrupt range without any actual hardware attached. This change moves the guest interrupt range after the core local interrupt range to avoid clash. Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual interrupt and IRQ filtering support.") Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.") Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240520125157.311503-3-rkanwal@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Extend virtual irq csrs masks to be 64 bit wide.Rajnesh Kanwal
AIA extends the width of all IRQ CSRs to 64bit even in 32bit systems by adding missing half CSRs. This seems to be missed while adding support for virtual IRQs. The whole logic seems to be correct except the width of the masks. Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual interrupt and IRQ filtering support.") Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.") Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240520125157.311503-2-rkanwal@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-24Merge tag 'pull-maintainer-june24-240624-1' of ↵Richard Henderson
https://gitlab.com/stsquad/qemu into staging maintainer updates (plugins, gdbstub): - add missing include guard comment to gdbstub.h - move gdbstub enums into separate header - move qtest_[get|set]_virtual_clock functions - allow plugins to manipulate the virtual clock - introduce an Instructions Per Second plugin - fix inject_mem_cb rw mask tests - allow qemu_plugin_vcpu_mem_cb to shortcut when no memory cbs # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmZ5OjoACgkQ+9DbCVqe # KkQPlwf/VK673BAjYktuCLnf3DgWvIkkiHWwzBREP5MmseUloLjK2CQPLY/xWZED # pbA/1OSzHViD/mvG5wTxwef36b9PIleWj5/YwBxGlrb/rh6hCd9004pZK4EMI3qU # 53SK8Qron8TIXjey6XfmAY8rcl030GsHr0Zqf5i2pZKE5g0iaGlM3Cwkpo0SxQsu # kMNqiSs9NzX7LxB+YeuAauIvC1YA2F/MGTXeFCTtO9Beyp5oV7oOI+2zIvLjlG5M # Z5hKjG/STkNOteoIBGZpe1+QNpoGHSBoGE3nQnGpXb82iLx1KVBcKuQ6GoWGv1Wo # hqiSh9kJX479l0mLML+IzaDsgSglbg== # =pvWx # -----END PGP SIGNATURE----- # gpg: Signature made Mon 24 Jun 2024 02:19:54 AM PDT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] * tag 'pull-maintainer-june24-240624-1' of https://gitlab.com/stsquad/qemu: accel/tcg: Avoid unnecessary call overhead from qemu_plugin_vcpu_mem_cb plugins: fix inject_mem_cb rw masking contrib/plugins: add Instructions Per Second (IPS) example for cost modeling plugins: add migration blocker plugins: add time control API qtest: move qtest_{get, set}_virtual_clock to accel/qtest/qtest.c sysemu: generalise qtest_warp_clock as qemu_clock_advance_virtual_time qtest: use cpu interface in qtest_clock_warp sysemu: add set_virtual_time to accel ops plugins: Ensure register handles are not NULL gdbstub: move enums into separate header include/exec: add missing include guard comment Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-24gdbstub: move enums into separate headerAlex Bennée
This is an experiment to further reduce the amount we throw into the exec headers. It might not be as useful as I initially thought because just under half of the users also need gdbserver_start(). Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240620152220.2192768-3-alex.bennee@linaro.org>
2024-06-24target/s390x: Add a CONFIG switch to disable legacy CPUsThomas Huth
The oldest model that IBM still supports is the z13. Considering that each generation can "emulate" the previous two generations in hardware (via the "IBC" feature of the CPUs), this means that everything that is older than z114/196 is not an officially supported CPU model anymore. The Linux kernel still support the z10, so if we also take this into account, everything older than that can definitely be considered as a legacy CPU model. For downstream builds of QEMU, we would like to be able to disable these legacy CPUs in the build. Thus add a CONFIG switch that can be used to disable them (and old machine types that use them by default). Message-Id: <20240614125019.588928-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-06-24target/s390x/arch_dump: use correct byte order for pidOmar Sandoval
The pid field of prstatus needs to be big endian like all of the other fields. Fixes: f738f296eaae ("s390x/arch_dump: pass cpuid into notes sections") Signed-off-by: Omar Sandoval <osandov@osandov.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <5929f76d536d355afd04af51bf293695a1065118.1718771802.git.osandov@osandov.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-06-19Merge tag 'pull-tcg-20240619' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson
tcg/loongarch64: Support 64- and 256-bit vectors tcg/loongarch64: Fix tcg_out_movi vs some pcrel pointers util/bufferiszero: Split out host include files util/bufferiszero: Add loongarch64 vector acceleration accel/tcg: Fix typo causing tb->page_addr[1] to not be recorded target/sparc: use signed denominator in sdiv helper linux-user: Make TARGET_NR_setgroups affect only the current thread # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmZzRoMdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9Y7gf/ZUTGjCUdAO7W7J5e # Z3JLUNOfUHO6PxoE05963XJc+APwKiuL6Yo2bnJo6km7WM50CoaX9/7L9CXD7STg # s3eUJ2p7FfvOADZgO373nqRrB/2mhvoywhDbVJBl+NcRvRUDW8rMqrlSKIAwDIsC # kwwTWlCfpBSlUgm/c6yCVmt815+sGUPD2k/p+pIzAVUG6fGYAosC2fwPzPajiDGX # Q+obV1fryKq2SRR2dMnhmPRtr3pQBBkISLuTX6xNM2+CYhYqhBrAlQaOEGhp7Dx3 # ucKjvQFpHgPOSdQxb/HaDv81A20ZUQaydiNNmuKQcTtMx3MsQFR8NyVjH7L+fbS8 # JokjaQ== # =yVKz # -----END PGP SIGNATURE----- # gpg: Signature made Wed 19 Jun 2024 01:58:43 PM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-tcg-20240619' of https://gitlab.com/rth7680/qemu: (24 commits) tcg/loongarch64: Fix tcg_out_movi vs some pcrel pointers target/sparc: use signed denominator in sdiv helper linux-user: Make TARGET_NR_setgroups affect only the current thread accel/tcg: Fix typo causing tb->page_addr[1] to not be recorded util/bufferiszero: Add loongarch64 vector acceleration util/bufferiszero: Split out host include files tcg/loongarch64: Enable v256 with LASX tcg/loongarch64: Support LASX in tcg_out_vec_op tcg/loongarch64: Split out vdvjukN in tcg_out_vec_op tcg/loongarch64: Remove temp_vec from tcg_out_vec_op tcg/loongarch64: Support LASX in tcg_out_{mov,ld,st} tcg/loongarch64: Split out vdvjvk in tcg_out_vec_op tcg/loongarch64: Support LASX in tcg_out_addsub_vec tcg/loongarch64: Simplify tcg_out_addsub_vec tcg/loongarch64: Support LASX in tcg_out_dupi_vec tcg/loongarch64: Use tcg_out_dup_vec in tcg_out_dupi_vec tcg/loongarch64: Support LASX in tcg_out_dupm_vec tcg/loongarch64: Support LASX in tcg_out_dup_vec tcg/loongarch64: Simplify tcg_out_dup_vec util/loongarch64: Detect LASX vector support ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19target/sparc: use signed denominator in sdiv helperClément Chigot
The result has to be done with the signed denominator (b32) instead of the unsigned value passed in argument (b). Cc: qemu-stable@nongnu.org Fixes: 1326010322d6 ("target/sparc: Remove CC_OP_DIV") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2319 Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240606144331.698361-1-chigot@adacore.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19target/s390x: Use s390_skeys_get|set() helperPhilippe Mathieu-Daudé
Commit c9274b6bf0 ("target/s390x: start moving TCG-only code to tcg/") moved mem_helper.c, but the trace-events file is still in the parent directory, so is the generated trace.h. Call the s390_skeys_get|set() helper, removing the need for the trace event shared with the tcg/ sub-directory, fixing the following build failure: In file included from ../target/s390x/tcg/mem_helper.c:33: ../target/s390x/tcg/trace.h:1:10: fatal error: 'trace/trace-target_s390x_tcg.h' file not found #include "trace/trace-target_s390x_tcg.h" Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20240613104415.9643-3-philmd@linaro.org>
2024-06-19target/i386: Remove X86CPU::kvm_no_smi_migration fieldPhilippe Mathieu-Daudé
X86CPU::kvm_no_smi_migration was only used by the pc-i440fx-2.3 machine, which got removed. Remove it and simplify kvm_put_vcpu_events(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240617071118.60464-23-philmd@linaro.org>
2024-06-19target/i386/kvm: Remove x86_cpu_change_kvm_default() and 'kvm-cpu.h'Philippe Mathieu-Daudé
x86_cpu_change_kvm_default() was only used out of kvm-cpu.c by the pc-i440fx-2.1 machine, which got removed. Make it static, and remove its declaration. "kvm-cpu.h" is now empty, remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240617071118.60464-10-philmd@linaro.org>
2024-06-17target/i386: SEV: do not assume machine->cgs is SEVPaolo Bonzini
There can be other confidential computing classes that are not derived from sev-common. Avoid aborting when encountering them. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-15 10:51:12 +0000