slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2022-01-21	target/riscv: Support virtual time context synchronization	Yifei Jiang
2022-01-21	target/riscv: Implement virtual time adjusting with vm state changing	Yifei Jiang
2022-01-21	target/riscv: Add kvm_riscv_get/put_regs_timer	Yifei Jiang
2022-01-21	target/riscv: Add host cpu type	Yifei Jiang
2022-01-21	target/riscv: Handle KVM_EXIT_RISCV_SBI exit	Yifei Jiang
2022-01-21	target/riscv: Support setting external interrupt by KVM	Yifei Jiang
2022-01-21	target/riscv: Support start kernel directly by KVM	Yifei Jiang
2022-01-21	target/riscv: Implement kvm_arch_put_registers	Yifei Jiang
2022-01-21	target/riscv: Implement kvm_arch_get_registers	Yifei Jiang
2022-01-21	target/riscv: Implement function kvm_arch_init_vcpu	Yifei Jiang
2022-01-21	target/riscv: Add target/riscv/kvm.c to place the public kvm interface	Yifei Jiang
2022-01-20	hw/arm/virt: KVM: Enable PAuth when supported by the host	Marc Zyngier
2022-01-19	Merge remote-tracking branch 'remotes/thuth-gitlab/tags/pull-request-2022-01-...	Peter Maydell
2022-01-18	s390x: sigp: Reorder the SIGP STOP code	Eric Farman
2022-01-18	target/ppc: Fix 7448 support	Cédric Le Goater
2022-01-18	target/ppc: Finish removal of 401/403 CPUs	Cédric Le Goater
2022-01-18	target/ppc: Remove last user of .load_state_old	Cédric Le Goater
2022-01-17	target/s390x: Fix shifting 32-bit values for more than 31 bits	Ilya Leoshkevich
2022-01-17	target/s390x: Fix cc_calc_sla_64() missing overflows	Ilya Leoshkevich
2022-01-17	target/s390x: Fix SRDA CC calculation	Ilya Leoshkevich
2022-01-17	target/s390x: Fix SLDA sign bit index	Ilya Leoshkevich
2022-01-13	Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...	Peter Maydell
2022-01-13	Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220112' into s...	Peter Maydell
2022-01-12	KVM: x86: ignore interrupt_bitmap field of KVM_GET/SET_SREGS	Paolo Bonzini
2022-01-12	KVM: use KVM_{GET\|SET}_SREGS2 when supported.	Maxim Levitsky
2022-01-12	target/ppc: Set the correct endianness for powernv memory dumps	Fabiano Rosas
2022-01-12	target/ppc: Introduce a wrapper for powerpc_excp	Fabiano Rosas
2022-01-12	target/ppc: Use ppc_interrupts_little_endian in powerpc_excp	Fabiano Rosas
2022-01-12	target/ppc: Add MSR_ILE support to ppc_interrupts_little_endian	Fabiano Rosas
2022-01-12	target/ppc: Add HV support to ppc_interrupts_little_endian	Fabiano Rosas
2022-01-12	target/ppc: powerpc_excp: Group unimplemented exceptions	Fabiano Rosas
2022-01-12	target/ppc: powerpc_excp: Keep 60x/7x5 soft MMU logs active	Fabiano Rosas
2022-01-12	target/ppc: powerpc_excp: Extract software TLB logging into a function	Fabiano Rosas
2022-01-12	target/ppc: Add extra float instructions to POWER5P processors	Cédric Le Goater
2022-01-12	target/ppc: Add popcntb instruction to POWER5+ processors	Cédric Le Goater
2022-01-11	target/mips: Extract trap code into env->error_code	Richard Henderson
2022-01-11	target/mips: Extract break code into env->error_code	Richard Henderson
2022-01-09	target/m68k: don't word align SP in stack frame if M68K_FEATURE_UNALIGNED_DAT...	Mark Cave-Ayland
2022-01-08	target/riscv: Implement the stval/mtval illegal instruction	Alistair Francis
2022-01-08	target/riscv: Fixup setting GVA	Alistair Francis
2022-01-08	target/riscv: Set the opcode in DisasContext	Alistair Francis
2022-01-08	target/riscv: actual functions to realize crs 128-bit insns	Frédéric Pétrot
2022-01-08	target/riscv: modification of the trans_csrxx for 128-bit support	Frédéric Pétrot
2022-01-08	target/riscv: helper functions to wrap calls to 128-bit csr insns	Frédéric Pétrot
2022-01-08	target/riscv: adding high part of some csrs	Frédéric Pétrot
2022-01-08	target/riscv: support for 128-bit M extension	Frédéric Pétrot
2022-01-08	target/riscv: support for 128-bit arithmetic instructions	Frédéric Pétrot
2022-01-08	target/riscv: support for 128-bit shift instructions	Frédéric Pétrot
2022-01-08	target/riscv: support for 128-bit U-type instructions	Frédéric Pétrot
2022-01-08	target/riscv: support for 128-bit bitwise instructions	Frédéric Pétrot