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AgeCommit message (Expand)Author
2017-02-14target/openrisc: Put SR[OVE] in TB flagsRichard Henderson
2017-02-14target/openrisc: Streamline arithmetic and OVERichard Henderson
2017-02-14target/openrisc: Rationalize immediate extractionRichard Henderson
2017-02-14target/openrisc: Tidy insn dumpingRichard Henderson
2017-02-14target/openrisc: Implement lwa, swaRichard Henderson
2017-02-14target/openrisc: Fix exception handling status registersStafford Horne
2017-02-14target/openrisc: Rename the cpu from or32 to or1kRichard Henderson
2017-02-10target-arm: Enable vPMU support under TCG modeWei Huang
2017-02-10target-arm: Add support for PMU register PMINTENSET_EL1Wei Huang
2017-02-10target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0Wei Huang
2017-02-10target-arm: Add support for PMU register PMSELR_EL0Wei Huang
2017-02-07target/arm: A32, T32: Create Instruction Syndromes for Data AbortsPeter Maydell
2017-02-07target/arm: Abstract out pbit/wbit tests in ARM ldr/str decodePeter Maydell
2017-02-07arm: Correctly handle watchpoints for BE32 CPUsJulian Brown
2017-02-07Fix Thumb-1 BE32 execution and disassembly.Julian Brown
2017-02-07target/arm: Add cfgend parameter for ARM CPU selection.Julian Brown
2017-02-06target/hppa: Fix gdb_write_registerRichard Henderson
2017-02-06target/hppa: Tidy do_cbranchRichard Henderson
2017-02-02Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170202' into...Peter Maydell
2017-02-02ppc/kvm: Handle the "family" CPU via alias instead of registering new typesThomas Huth
2017-02-02target/ppc/mmu_hash64: Fix incorrect shift value in amr calculationSuraj Jitindar Singh
2017-02-02target/ppc/mmu_hash64: Fix printing unsigned as signed intSuraj Jitindar Singh
2017-02-02tcg/POWER9: NOOP the cp_abort instructionSuraj Jitindar Singh
2017-02-02target/ppc/debug: Print LPCR register value if register existsSuraj Jitindar Singh
2017-02-02target-ppc: Add xststdc[sp, dp, qp] instructionsNikunj A Dadhania
2017-02-02target-ppc: Add xvtstdc[sp,dp] instructionsNikunj A Dadhania
2017-02-01arm: add trailing ; after MISMATCH_CHECKMichael S. Tsirkin
2017-02-01arm: better stub version for MISMATCH_CHECKMichael S. Tsirkin
2017-01-31target/ppc/cpu-models: Fix/remove bad CPU aliasesThomas Huth
2017-01-31target/ppc: Remove unused POWERPC_FAMILY(POWER)Thomas Huth
2017-01-31spapr: clock should count only if vm is runningLaurent Vivier
2017-01-31target/ppc: Add pcr_supported to POWER9 cpu class definitionSuraj Jitindar Singh
2017-01-31powerpc/cpu-models: rename ISAv3.00 logical PVR definitionSuraj Jitindar Singh
2017-01-31target-ppc: Add xvcv[hpsp, sphp] instructionsNikunj A Dadhania
2017-01-31target-ppc: Add xsmulqp instructionBharata B Rao
2017-01-31target-ppc: Add xsdivqp instructionBharata B Rao
2017-01-31target-ppc: Add xscvsdqp and xscvudqp instructionsBharata B Rao
2017-01-31target-ppc: Use ppc_vsr_t.f128 in xscmp[o,u,exp]qpBharata B Rao
2017-01-31ppc: Implement bcdutrunc. instructionJose Ricardo Ziviani
2017-01-31ppc: Implement bcdtrunc. instructionJose Ricardo Ziviani
2017-01-31target-ppc: Add xscvqps[d,w]z instructionsBharata B Rao
2017-01-31target-ppc: Add xvxsigdp instructionNikunj A Dadhania
2017-01-31target-ppc: Add xvxsigsp instructionNikunj A Dadhania
2017-01-31target-ppc: Add xvxexpdp instructionNikunj A Dadhania
2017-01-31target-ppc: Add xvxexpsp instructionNikunj A Dadhania
2017-01-31target-ppc: Add xviexpdp instructionNikunj A Dadhania
2017-01-31target-ppc: Add xviexpsp instructionNikunj A Dadhania
2017-01-31target-ppc: Add xsiexpqp instructionNikunj A Dadhania
2017-01-31target-ppc: Add xsiexpdp instructionNikunj A Dadhania
2017-01-31ppc: Implement bcdsr. instructionJose Ricardo Ziviani
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