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AgeCommit message (Expand)Author
2024-05-07target/i386: use TSTEQ/TSTNE to check flagsPaolo Bonzini
2024-05-07target/i386: use TSTEQ/TSTNE to test low bitsPaolo Bonzini
2024-05-07target/i386: Fix CPUID encoding of Fn8000001E_ECXBabu Moger
2024-05-06target/sh4: Update DisasContextBase.insn_startRichard Henderson
2024-05-06Merge tag 'qemu-sparc-20240506' of https://github.com/mcayland/qemu into stagingRichard Henderson
2024-05-06Merge tag 'accel-20240506' of https://github.com/philmd/qemu into stagingRichard Henderson
2024-05-06Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson
2024-05-06accel/tcg: Access tcg_cflags with getter / setterPhilippe Mathieu-Daudé
2024-05-06exec/cpu: Extract page-protection definitions to page-protection.hPhilippe Mathieu-Daudé
2024-05-06exec/cpu: Rename PAGE_BITS macro to PAGE_RWXBALATON Zoltan
2024-05-05Hexagon (target/hexagon) Remove hex_common.read_attribs_fileTaylor Simpson
2024-05-05Hexagon (target/hexagon) Remove gen_shortcode.pyTaylor Simpson
2024-05-05Hexagon (target/hexagon) Remove gen_op_regs.pyTaylor Simpson
2024-05-05Hexagon (target/hexagon) Remove uses of op_regs_generated.h.incTaylor Simpson
2024-05-05Hexagon (target/hexagon) Mark has_pred_dest in trans functionsTaylor Simpson
2024-05-05Hexagon (target/hexagon) Mark dest_idx in trans functionsTaylor Simpson
2024-05-05Hexagon (target/hexagon) Mark new_read_idx in trans functionsTaylor Simpson
2024-05-05Hexagon (target/hexagon) Add is_old/is_new to Register classTaylor Simpson
2024-05-05Hexagon (target/hexagon) Only pass env to generated helper when neededTaylor Simpson
2024-05-05Hexagon (target/hexagon) Pass SP explicitly to helpers that need itTaylor Simpson
2024-05-05Hexagon (target/hexagon) Pass P0 explicitly to helpers that need itTaylor Simpson
2024-05-05Hexagon (target/hexagon) Enable more short-circuit packets (HVX)Taylor Simpson
2024-05-05Hexagon (target/hexagon) Enable more short-circuit packets (scalar core)Taylor Simpson
2024-05-05Hexagon (target/hexagon) Analyze reads before writesTaylor Simpson
2024-05-05target/sparc: Split out do_ms16bRichard Henderson
2024-05-05target/sparc: Fix FPMERGERichard Henderson
2024-05-05target/sparc: Fix FMULD8*X16Richard Henderson
2024-05-05target/sparc: Fix FMUL8x16A{U,L}Richard Henderson
2024-05-05target/sparc: Fix FMUL8x16Richard Henderson
2024-05-05target/sparc: Fix FEXPANDRichard Henderson
2024-05-05target/sparc/cpu: Avoid spaces by default in the CPU namesThomas Huth
2024-05-05target/sparc/cpu: Rename the CPU models with a "+" in their namesThomas Huth
2024-05-04target/alpha: Implement CF_PCRELRichard Henderson
2024-05-04target/alpha: Split out gen_pc_dispRichard Henderson
2024-05-04target/alpha: Split out gen_goto_tbRichard Henderson
2024-05-04target/alpha: Simplify gen_bcond_internal()Philippe Mathieu-Daudé
2024-05-04target/alpha: Return DISAS_NORETURN onceRichard Henderson
2024-05-04target/alpha: Inline DISAS_PC_UPDATED and return DISAS_NORETURNRichard Henderson
2024-05-04target/alpha: Use DISAS_NEXT definition instead of magic '0' valueRichard Henderson
2024-05-04target/alpha: Hoist branch shift to initial decodeRichard Henderson
2024-05-04target/alpha: Use cpu_env in preference to ALPHA_CPURichard Henderson
2024-05-03Merge tag 'accel-sh4-ui-20240503' of https://github.com/philmd/qemu into stagingRichard Henderson
2024-05-03target/sh4: Rename TCGv variables as manual for SUBV opcodePhilippe Mathieu-Daudé
2024-05-03target/sh4: Rename TCGv variables as manual for ADDV opcodePhilippe Mathieu-Daudé
2024-05-03target/sh4: Fix SUBV opcodePhilippe Mathieu-Daudé
2024-05-03target/sh4: Fix ADDV opcodePhilippe Mathieu-Daudé
2024-05-03target/i386: Introduce SapphireRapids-v3 to add missing featuresLei Wang
2024-05-03ppc: switch boards to "default y"Paolo Bonzini
2024-05-03meson: make target endianneess available to KconfigPaolo Bonzini
2024-05-03i386: switch boards to "default y"Paolo Bonzini
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