| Age | Commit message (Expand) | Author |
|---|
| 2024-05-24 | target/ppc: larx/stcx generation need only apply DEF_MEMOP() once | Nicholas Piggin |
| 2024-05-24 | target/ppc: Add migration support for BHRB | Glenn Miles |
| 2024-05-24 | target/ppc: Add clrbhrb and mfbhrbe instructions | Glenn Miles |
| 2024-05-24 | target/ppc: Add recording of taken branches to BHRB | Glenn Miles |
| 2024-05-24 | target/ppc: Add new hflags to support BHRB | Glenn Miles |
| 2024-05-24 | target/ppc: Move VMX integer max/min instructions to decodetree. | Chinmay Rath |
| 2024-05-24 | target/ppc: Move VMX integer logical instructions to decodetree. | Chinmay Rath |
| 2024-05-24 | target/ppc: Move VMX storage access instructions to decodetree | Chinmay Rath |
| 2024-05-24 | target/ppc: Move logical fixed-point instructions to decodetree. | Chinmay Rath |
| 2024-05-24 | target/ppc: Move cmp{rb, eqb}, tw[i], td[i], isel instructions to decodetree. | Chinmay Rath |
| 2024-05-24 | target/ppc: Move div/mod fixed-point insns (64 bits operands) to decodetree. | Chinmay Rath |
| 2024-05-24 | target/ppc: Move multiply fixed-point insns (64-bit operands) to decodetree. | Chinmay Rath |
| 2024-05-24 | target/ppc: Move neg, darn, mod{sw, uw} to decodetree. | Chinmay Rath |
| 2024-05-24 | target/ppc: Move divw[u, e, eu] instructions to decodetree. | Chinmay Rath |
| 2024-05-24 | target/ppc: Make divw[u] handler method decodetree compatible. | Chinmay Rath |
| 2024-05-24 | target/ppc: Move mul{li, lw, lwo, hw, hwu} instructions to decodetree. | Chinmay Rath |
| 2024-05-24 | target/ppc: Move floating-point arithmetic instructions to decodetree. | Chinmay Rath |
| 2024-05-24 | target/ppc: Merge various fpu helpers | Chinmay Rath |
| 2024-05-24 | target/ppc: Add ISA v3.1 variants of sync instruction | Nicholas Piggin |
| 2024-05-24 | target/ppc: Fix embedded memory barriers | Nicholas Piggin |
| 2024-05-24 | target/ppc: Move sync instructions to decodetree | Nicholas Piggin |
| 2024-05-24 | target/ppc: Fix broadcast tlbie synchronisation | Nicholas Piggin |
| 2024-05-24 | spapr: avoid overhead of finding vhyp class in critical operations | Nicholas Piggin |
| 2024-05-23 | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging | Richard Henderson |
| 2024-05-23 | target/loongarch: Add loongarch vector property unconditionally | Bibo Mao |
| 2024-05-23 | target/loongarch/kvm: fpu save the vreg registers high 192bit | Song Gao |
| 2024-05-23 | target/loongarch/kvm: Fix VM recovery from disk failures | Song Gao |
| 2024-05-22 | target-i386: hyper-v: Correct kvm_hv_handle_exit return value | donsheng |
| 2024-05-22 | i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 2... | Zhao Liu |
| 2024-05-22 | i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[4] | Zhao Liu |
| 2024-05-22 | i386: Add cache topology info in CPUCacheInfo | Zhao Liu |
| 2024-05-22 | i386/cpu: Introduce module-id to X86CPU | Zhao Liu |
| 2024-05-22 | i386: Expose module level in CPUID[0x1F] | Zhao Liu |
| 2024-05-22 | i386: Support modules_per_die in X86CPUTopoInfo | Zhao Liu |
| 2024-05-22 | i386: Introduce module level cpu topology to CPUX86State | Zhao Liu |
| 2024-05-22 | i386/cpu: Decouple CPUID[0x1F] subleaf with specific topology level | Zhao Liu |
| 2024-05-22 | i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] | Zhao Liu |
| 2024-05-22 | i386/cpu: Introduce bitmap to cache available CPU topology levels | Zhao Liu |
| 2024-05-22 | i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid() | Zhao Liu |
| 2024-05-22 | i386/cpu: Use APIC ID info get NumSharingCache for CPUID[0x8000001D].EAX[bits... | Zhao Liu |
| 2024-05-22 | i386/cpu: Use APIC ID info to encode cache topo in CPUID[4] | Zhao Liu |
| 2024-05-22 | i386/cpu: Fix i/d-cache topology to core level for Intel CPU | Zhao Liu |
| 2024-05-22 | target/i386: add control bits support for LAM | Binbin Wu |
| 2024-05-22 | target/i386: add support for LAM in CPUID enumeration | Robert Hoo |
| 2024-05-22 | target/i386: clean up AAM/AAD | Paolo Bonzini |
| 2024-05-22 | target/i386: generate simpler code for ROL/ROR with immediate count | Paolo Bonzini |
| 2024-05-15 | Merge tag 'pull-hppa-20240515' of https://gitlab.com/rth7680/qemu into staging | Richard Henderson |
| 2024-05-15 | target/hppa: Log cpu state on return-from-interrupt | Richard Henderson |
| 2024-05-15 | target/hppa: Log cpu state at interrupt | Richard Henderson |
| 2024-05-15 | target/hppa: Implement CF_PCREL | Richard Henderson |
