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AgeCommit message (Expand)Author
2024-05-24target/ppc: larx/stcx generation need only apply DEF_MEMOP() onceNicholas Piggin
2024-05-24target/ppc: Add migration support for BHRBGlenn Miles
2024-05-24target/ppc: Add clrbhrb and mfbhrbe instructionsGlenn Miles
2024-05-24target/ppc: Add recording of taken branches to BHRBGlenn Miles
2024-05-24target/ppc: Add new hflags to support BHRBGlenn Miles
2024-05-24target/ppc: Move VMX integer max/min instructions to decodetree.Chinmay Rath
2024-05-24target/ppc: Move VMX integer logical instructions to decodetree.Chinmay Rath
2024-05-24target/ppc: Move VMX storage access instructions to decodetreeChinmay Rath
2024-05-24target/ppc: Move logical fixed-point instructions to decodetree.Chinmay Rath
2024-05-24target/ppc: Move cmp{rb, eqb}, tw[i], td[i], isel instructions to decodetree.Chinmay Rath
2024-05-24target/ppc: Move div/mod fixed-point insns (64 bits operands) to decodetree.Chinmay Rath
2024-05-24target/ppc: Move multiply fixed-point insns (64-bit operands) to decodetree.Chinmay Rath
2024-05-24target/ppc: Move neg, darn, mod{sw, uw} to decodetree.Chinmay Rath
2024-05-24target/ppc: Move divw[u, e, eu] instructions to decodetree.Chinmay Rath
2024-05-24target/ppc: Make divw[u] handler method decodetree compatible.Chinmay Rath
2024-05-24target/ppc: Move mul{li, lw, lwo, hw, hwu} instructions to decodetree.Chinmay Rath
2024-05-24target/ppc: Move floating-point arithmetic instructions to decodetree.Chinmay Rath
2024-05-24target/ppc: Merge various fpu helpersChinmay Rath
2024-05-24target/ppc: Add ISA v3.1 variants of sync instructionNicholas Piggin
2024-05-24target/ppc: Fix embedded memory barriersNicholas Piggin
2024-05-24target/ppc: Move sync instructions to decodetreeNicholas Piggin
2024-05-24target/ppc: Fix broadcast tlbie synchronisationNicholas Piggin
2024-05-24spapr: avoid overhead of finding vhyp class in critical operationsNicholas Piggin
2024-05-23Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson
2024-05-23target/loongarch: Add loongarch vector property unconditionallyBibo Mao
2024-05-23target/loongarch/kvm: fpu save the vreg registers high 192bitSong Gao
2024-05-23target/loongarch/kvm: Fix VM recovery from disk failuresSong Gao
2024-05-22target-i386: hyper-v: Correct kvm_hv_handle_exit return valuedonsheng
2024-05-22i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 2...Zhao Liu
2024-05-22i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[4]Zhao Liu
2024-05-22i386: Add cache topology info in CPUCacheInfoZhao Liu
2024-05-22i386/cpu: Introduce module-id to X86CPUZhao Liu
2024-05-22i386: Expose module level in CPUID[0x1F]Zhao Liu
2024-05-22i386: Support modules_per_die in X86CPUTopoInfoZhao Liu
2024-05-22i386: Introduce module level cpu topology to CPUX86StateZhao Liu
2024-05-22i386/cpu: Decouple CPUID[0x1F] subleaf with specific topology levelZhao Liu
2024-05-22i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB]Zhao Liu
2024-05-22i386/cpu: Introduce bitmap to cache available CPU topology levelsZhao Liu
2024-05-22i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid()Zhao Liu
2024-05-22i386/cpu: Use APIC ID info get NumSharingCache for CPUID[0x8000001D].EAX[bits...Zhao Liu
2024-05-22i386/cpu: Use APIC ID info to encode cache topo in CPUID[4]Zhao Liu
2024-05-22i386/cpu: Fix i/d-cache topology to core level for Intel CPUZhao Liu
2024-05-22target/i386: add control bits support for LAMBinbin Wu
2024-05-22target/i386: add support for LAM in CPUID enumerationRobert Hoo
2024-05-22target/i386: clean up AAM/AADPaolo Bonzini
2024-05-22target/i386: generate simpler code for ROL/ROR with immediate countPaolo Bonzini
2024-05-15Merge tag 'pull-hppa-20240515' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson
2024-05-15target/hppa: Log cpu state on return-from-interruptRichard Henderson
2024-05-15target/hppa: Log cpu state at interruptRichard Henderson
2024-05-15target/hppa: Implement CF_PCRELRichard Henderson