Age | Commit message (Expand) | Author |
2024-06-04 | Merge tag 'hw-misc-accel-20240604' of https://github.com/philmd/qemu into sta... | Richard Henderson |
2024-06-04 | cpu: move Qemu[Thread|Cond] setup into common code | Alex Bennée |
2024-06-04 | target/i386/kvm: Improve KVM_EXIT_NOTIFY warnings | Richard Henderson |
2024-06-04 | target/arm: Replace sprintf() by snprintf() | Philippe Mathieu-Daudé |
2024-06-04 | target/mips: Remove unused 'hw/misc/mips_itu.h' header | Philippe Mathieu-Daudé |
2024-06-04 | target/riscv: Restrict riscv_cpu_do_interrupt() to sysemu | Philippe Mathieu-Daudé |
2024-06-04 | target/riscv: Restrict 'rv128' machine to TCG accelerator | Philippe Mathieu-Daudé |
2024-06-04 | target/riscv: Remove unused 'instmap.h' header in translate.c | Philippe Mathieu-Daudé |
2024-06-03 | riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature() | Daniel Henrique Barboza |
2024-06-03 | target/riscv/kvm.c: Fix the hart bit setting of AIA | Yong-Xuan Wang |
2024-06-03 | target/riscv: rvzicbo: Fixup CBO extension register calculation | Alistair Francis |
2024-06-03 | target/riscv: Remove experimental prefix from "B" extension | Rob Bradford |
2024-06-03 | target/riscv: do not set mtval2 for non guest-page faults | Alexei Filippov |
2024-06-03 | target/riscv: prioritize pmp errors in raise_mmu_exception() | Daniel Henrique Barboza |
2024-06-03 | target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen in... | Max Chou |
2024-06-03 | target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w | Max Chou |
2024-06-03 | target/riscv: rvv: Check single width operator for vector fp widen instructions | Max Chou |
2024-06-03 | target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w ins... | Max Chou |
2024-06-03 | riscv: thead: Add th.sxstatus CSR emulation | Christoph Müllner |
2024-06-03 | target/riscv: Implement dynamic establishment of custom decoder | Huang Tao |
2024-06-03 | target/riscv/cpu.c: fix Zvkb extension config | Yangyu Chen |
2024-06-03 | target/riscv: Fix the element agnostic function problem | Huang Tao |
2024-06-03 | target/riscv: Relax vector register check in RISCV gdbstub | Jason Chien |
2024-06-03 | target/riscv: Add support for Zve64x extension | Jason Chien |
2024-06-03 | target/riscv: Add support for Zve32x extension | Jason Chien |
2024-06-03 | trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint | Daniel Henrique Barboza |
2024-06-03 | target/riscv/debug: set tval=pc in breakpoint exceptions | Daniel Henrique Barboza |
2024-06-03 | target/riscv/kvm: tolerate KVM disable ext errors | Daniel Henrique Barboza |
2024-06-03 | target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63 | Clément Léger |
2024-06-03 | target/riscv/kvm: implement SBI debug console (DBCN) calls | Daniel Henrique Barboza |
2024-06-03 | target/riscv: Raise exceptions on wrs.nto | Andrew Jones |
2024-06-03 | target/riscv/kvm: Fix exposure of Zkr | Andrew Jones |
2024-05-30 | target/arm: Implement FEAT WFxT and enable for '-cpu max' | Peter Maydell |
2024-05-30 | accel/tcg: Make TCGCPUOps::cpu_exec_halt return bool for whether to halt | Peter Maydell |
2024-05-30 | target/arm: Disable SVE extensions when SVE is disabled | Marcin Juszkiewicz |
2024-05-30 | target/arm: Convert FCSEL to decodetree | Richard Henderson |
2024-05-30 | target/arm: Convert FMADD, FMSUB, FNMADD, FNMSUB to decodetree | Richard Henderson |
2024-05-30 | target/arm: Convert SQDMULH, SQRDMULH to decodetree | Richard Henderson |
2024-05-30 | target/arm: Tidy SQDMULH, SQRDMULH (vector) | Richard Henderson |
2024-05-30 | target/arm: Convert MLA, MLS to decodetree | Richard Henderson |
2024-05-30 | target/arm: Convert MUL, PMUL to decodetree | Richard Henderson |
2024-05-30 | target/arm: Convert SABA, SABD, UABA, UABD to decodetree | Richard Henderson |
2024-05-30 | target/arm: Convert SMAX, SMIN, UMAX, UMIN to decodetree | Richard Henderson |
2024-05-30 | target/arm: Convert SRHADD, URHADD to decodetree | Richard Henderson |
2024-05-30 | target/arm: Convert SRHADD, URHADD to gvec | Richard Henderson |
2024-05-30 | target/arm: Convert SHSUB, UHSUB to decodetree | Richard Henderson |
2024-05-30 | target/arm: Convert SHSUB, UHSUB to gvec | Richard Henderson |
2024-05-30 | target/arm: Convert SHADD, UHADD to decodetree | Richard Henderson |
2024-05-30 | target/arm: Convert SHADD, UHADD to gvec | Richard Henderson |
2024-05-30 | target/arm: Use TCG_COND_TSTNE in gen_cmtst_vec | Richard Henderson |