slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2021-12-20	target/riscv: rvv-1.0: count population in mask instruction	Frank Chang
2021-12-20	target/riscv: rvv-1.0: floating-point classify instructions	Frank Chang
2021-12-20	target/riscv: rvv-1.0: floating-point square-root instruction	Frank Chang
2021-12-20	target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation	Frank Chang
2021-12-20	target/riscv: rvv-1.0: update vext_max_elems() for load/store insns	Frank Chang
2021-12-20	target/riscv: rvv-1.0: load/store whole register instructions	Frank Chang
2021-12-20	target/riscv: rvv-1.0: fault-only-first unit stride load	Frank Chang
2021-12-20	target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store i...	Frank Chang
2021-12-20	target/riscv: rvv-1.0: index load and store instructions	Frank Chang
2021-12-20	target/riscv: rvv-1.0: stride load and store instructions	Frank Chang
2021-12-20	target/riscv: rvv-1.0: configure instructions	Frank Chang
2021-12-20	target/riscv: rvv-1.0: remove amo operations instructions	Frank Chang
2021-12-20	target/riscv: rvv:1.0: add translation-time nan-box helper function	Frank Chang
2021-12-20	target/riscv: introduce more imm value modes in translator functions	Frank Chang
2021-12-20	target/riscv: rvv-1.0: update check functions	Frank Chang
2021-12-20	target/riscv: rvv-1.0: add VMA and VTA	Frank Chang
2021-12-20	target/riscv: rvv-1.0: add fractional LMUL	Frank Chang
2021-12-20	target/riscv: rvv-1.0: remove MLEN calculations	Frank Chang
2021-12-20	target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers	Frank Chang
2021-12-20	target/riscv: rvv-1.0: add vlenb register	Greentime Hu
2021-12-20	target/riscv: rvv-1.0: add vcsr register	LIU Zhiwei
2021-12-20	target/riscv: rvv-1.0: remove rvv related codes from fcsr registers	Frank Chang
2021-12-20	target/riscv: rvv-1.0: add translation-time vector context status	Frank Chang
2021-12-20	target/riscv: rvv-1.0: introduce writable misa.v field	Frank Chang
2021-12-20	target/riscv: rvv-1.0: add sstatus VS field	LIU Zhiwei
2021-12-20	target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty	Frank Chang
2021-12-20	target/riscv: rvv-1.0: add mstatus VS field	LIU Zhiwei
2021-12-20	target/riscv: Use FIELD_EX32() to extract wd field	Frank Chang
2021-12-20	target/riscv: drop vector 0.7.1 and add 1.0 support	Frank Chang
2021-12-20	target/riscv: zfh: add Zfhmin cpu property	Frank Chang
2021-12-20	target/riscv: zfh: implement zfhmin extension	Frank Chang
2021-12-20	target/riscv: zfh: add Zfh cpu property	Frank Chang
2021-12-20	target/riscv: zfh: half-precision floating-point classify	Kito Cheng
2021-12-20	target/riscv: zfh: half-precision floating-point compare	Kito Cheng
2021-12-20	target/riscv: zfh: half-precision convert and move	Kito Cheng
2021-12-20	target/riscv: zfh: half-precision computational	Kito Cheng
2021-12-20	target/riscv: zfh: half-precision load and store	Kito Cheng
2021-12-17	Merge tag 'trivial-branch-for-7.0-pull-request' of https://gitlab.com/laurent...	Richard Henderson
2021-12-17	Merge tag 'pull-ppc-20211217' of https://github.com/legoater/qemu into staging	Richard Henderson
2021-12-17	PPC64/TCG: Implement 'rfebb' instruction	Daniel Henrique Barboza
2021-12-17	target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event	Daniel Henrique Barboza
2021-12-17	target/ppc: enable PMU instruction count	Daniel Henrique Barboza
2021-12-17	target/ppc: enable PMU counter overflow with cycle events	Daniel Henrique Barboza
2021-12-17	target/ppc: PMU: update counters on MMCR1 write	Daniel Henrique Barboza
2021-12-17	target/ppc: PMU: update counters on PMCs r/w	Daniel Henrique Barboza
2021-12-17	target/ppc: PMU basic cycle count for pseries TCG	Daniel Henrique Barboza
2021-12-17	target/ppc: introduce PMUEventType and PMU overflow timers	Daniel Henrique Barboza
2021-12-17	Revert "target/ppc: Move SPR_DSISR setting to powerpc_excp"	Fabiano Rosas
2021-12-17	target/ppc: Fix e6500 boot	Fabiano Rosas
2021-12-17	target/ppc: move xscvqpdp to decodetree	Matheus Ferst