index
:
slackcoder/qemu
master
QEMU is a generic and open source machine & userspace emulator and virtualizer
Mirror
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
Age
Commit message (
Expand
)
Author
2021-12-23
target/hppa: Fix deposit assert from trans_shrpw_imm
Richard Henderson
2021-12-20
target/riscv: Enable bitmanip Zb[abcs] instructions
Vineet Gupta
2021-12-20
target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: update opivv_vadc_check() comment
Frank Chang
2021-12-20
target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...
Frank Chang
2021-12-20
target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
Frank Chang
2021-12-20
target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
Frank Chang
2021-12-20
target/riscv: rvv-1.0: add vsetivli instruction
Frank Chang
2021-12-20
target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
Frank Chang
2021-12-20
target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
Frank Chang
2021-12-20
target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...
Frank Chang
2021-12-20
target/riscv: gdb: support vector registers for rv64 & rv32
Hsiangkai Wang
2021-12-20
target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
Frank Chang
2021-12-20
target/riscv: rvv-1.0: implement vstart CSR
Frank Chang
2021-12-20
target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
Frank Chang
2021-12-20
target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
Frank Chang
2021-12-20
target/riscv: add "set round to odd" rounding mode helper function
Frank Chang
2021-12-20
target/riscv: rvv-1.0: widening floating-point/integer type-convert
Frank Chang
2021-12-20
target/riscv: rvv-1.0: floating-point/integer type-convert instructions
Frank Chang
2021-12-20
target/riscv: introduce floating-point rounding mode enum
Frank Chang
2021-12-20
target/riscv: rvv-1.0: floating-point min/max instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: remove integer extract instruction
Frank Chang
2021-12-20
target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
Frank Chang
2021-12-20
target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
Frank Chang
2021-12-20
target/riscv: rvv-1.0: single-width scaling shift instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: widening floating-point reduction instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: single-width floating-point reduction
Frank Chang
2021-12-20
target/riscv: rvv-1.0: narrowing fixed-point clip instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: floating-point slide instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: slide instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: mask-register logical instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: floating-point compare instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: integer comparison instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: single-width saturating add and subtract instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: widening integer multiply-add instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: narrowing integer right shift instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
Frank Chang
2021-12-20
target/riscv: rvv-1.0: single-width bit shift instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: single-width averaging add and subtract instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: integer extension instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: whole register move instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: floating-point scalar move instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: floating-point move instruction
Frank Chang
2021-12-20
target/riscv: rvv-1.0: integer scalar move instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: register gather instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: allow load element with sign-extended
Frank Chang
2021-12-20
target/riscv: rvv-1.0: element index instruction
Frank Chang
2021-12-20
target/riscv: rvv-1.0: iota instruction
Frank Chang
2021-12-20
target/riscv: rvv-1.0: set-X-first mask bit instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: find-first-set mask bit instruction
Frank Chang
[next]