aboutsummaryrefslogtreecommitdiff
path: root/target
AgeCommit message (Expand)Author
2023-06-05target/s390x: Fix LOCFHR taking the wrong half of R2Ilya Leoshkevich
2023-06-05target/s390x: Fix LCBB overwriting the top 32 bitsIlya Leoshkevich
2023-05-30target/arm: Explain why we need to select ARM_V7MFabiano Rosas
2023-05-30target/arm: Explicitly select short-format FSR for M-profilePeter Maydell
2023-05-28target/ppc: Add POWER9 DD2.2 modelNicholas Piggin
2023-05-28target/ppc: Merge COMPUTE_CLASS and COMPUTE_FPRFRichard Henderson
2023-05-28target/ppc: Use SMT4 small core chip type in POWER9/10 PVRsNicholas Piggin
2023-05-28spapr: Add SPAPR_CAP_AIL_MODE_3 for AIL mode 3 support for H_SET_MODE hcallNicholas Piggin
2023-05-27target/ppc: Alignment faults do not set DSISR in ISA v3.0 onwardNicholas Piggin
2023-05-27target/ppc: Fix width of some 32-bit SPRsNicholas Piggin
2023-05-27target/ppc: Fix fallback to MFSS for MFFS* instructions on pre 3.0 ISAsRichard Purdie
2023-05-26Merge tag 'pull-hex-20230526' of https://github.com/quic/qemu into stagingRichard Henderson
2023-05-26Hexagon: fix outdated `hex_new_*` commentsMatheus Tavares Bernardino
2023-05-26target/hexagon/*.py: clean up used 'toss' and 'numregs' varsMatheus Tavares Bernardino
2023-05-26Hexagon (target/hexagon) Fix assignment to tmp registersMarco Liebel
2023-05-26target/loongarch: Fix the vinsgr2vr/vpickve2gr instructions cause system core...Song Gao
2023-05-26target/loongarch: Fix LD/ST{LE/GT} instructions get wrong CSR_ERA and CSR_BADVSong Gao
2023-05-25Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson
2023-05-25target/i386: EPYC-Rome model without XSAVESMaksim Davydov
2023-05-23tcg: Remove DEBUG_DISASRichard Henderson
2023-05-23qemu/atomic128: Split atomic16_readRichard Henderson
2023-05-23target/s390x: Always use cpu_atomic_cmpxchgl_be_mmu in do_csstRichard Henderson
2023-05-23target/s390x: Use cpu_{ld,st}*_mmu in do_csstRichard Henderson
2023-05-23accel/tcg: Unify cpu_{ld,st}*_{be,le}_mmuRichard Henderson
2023-05-23target/s390x: Use tcg_gen_qemu_{ld,st}_i128 for LPQ, STPQRichard Henderson
2023-05-23target/ppc: Use tcg_gen_qemu_{ld,st}_i128 for LQARX, LQ, STQRichard Henderson
2023-05-19Revert "arm/kvm: add support for MTE"Peter Maydell
2023-05-18Merge tag 'pull-hex-20230518-1' of https://github.com/quic/qemu into stagingRichard Henderson
2023-05-18Hexagon (gdbstub): add HVX supportTaylor Simpson
2023-05-18Hexagon (gdbstub): fix p3:0 read and write via stubBrian Cain
2023-05-18Hexagon: add core gdbstub xml data for LLDBMatheus Tavares Bernardino
2023-05-18Hexagon (decode): look for pkts with multiple insns at the same slotMatheus Tavares Bernardino
2023-05-18Hexagon (iclass): update J4_hintjumpr slot constraintsMatheus Tavares Bernardino
2023-05-18Hexagon: list available CPUs with `-cpu help`Matheus Tavares Bernardino
2023-05-18Hexagon (target/hexagon/*.py): raise exception on reg parsing errorMatheus Tavares Bernardino
2023-05-18target/hexagon: fix = vs. == mishapPaolo Bonzini
2023-05-18Hexagon (target/hexagon) Additional instructions handled by idef-parserTaylor Simpson
2023-05-18Hexagon (target/hexagon) Move items to DisasContextTaylor Simpson
2023-05-18Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContextTaylor Simpson
2023-05-18Hexagon (target/hexagon) Move pred_written to DisasContextTaylor Simpson
2023-05-18Hexagon (target/hexagon) Move new_pred_value to DisasContextTaylor Simpson
2023-05-18Hexagon (target/hexagon) Move new_value to DisasContextTaylor Simpson
2023-05-18Hexagon (target/hexagon) Make special new_value for USRTaylor Simpson
2023-05-18Hexagon (target/hexagon) Add overrides for disabled idef-parser insnsTaylor Simpson
2023-05-18Hexagon (target/hexagon) Short-circuit more HVX single instruction packetsTaylor Simpson
2023-05-18Hexagon (target/hexagon) Short-circuit packet HVX writesTaylor Simpson
2023-05-18Hexagon (target/hexagon) Short-circuit packet predicate writesTaylor Simpson
2023-05-18Hexagon (target/hexagon) Short-circuit packet register writesTaylor Simpson
2023-05-18Hexagon (target/hexagon) Mark registers as read during packet analysisTaylor Simpson
2023-05-18Hexagon (target/hexagon) Don't overlap dest writes with source readsTaylor Simpson