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AgeCommit message (Expand)Author
2022-05-25Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson
2022-05-25i386: Hyper-V Direct TLB flush hypercallVitaly Kuznetsov
2022-05-25i386: Hyper-V Support extended GVA ranges for TLB flush hypercallsVitaly Kuznetsov
2022-05-25i386: Hyper-V XMM fast hypercall input featureVitaly Kuznetsov
2022-05-25i386: Hyper-V Enlightened MSR bitmap featureVitaly Kuznetsov
2022-05-25i386: Use hv_build_cpuid_leaf() for HV_CPUID_NESTED_FEATURESVitaly Kuznetsov
2022-05-25target/i386/kvm: Fix disabling MPX on "-cpu host" with MPX-capable hostMaciej S. Szmigiero
2022-05-24target/riscv: add zicsr/zifencei to isa_stringHongren (Zenithal) Zheng
2022-05-24target/riscv: Set [m|s]tval for both illegal and virtual instruction trapsAnup Patel
2022-05-24target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-modeAnup Patel
2022-05-24target/riscv: Fix csr number based privilege checkingAnup Patel
2022-05-24target/riscv: Fix typo of mimpid cpu optionFrank Chang
2022-05-24target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realizeWeiwei Li
2022-05-24target/riscv: Move/refactor ISA extension checksTsukasa OI
2022-05-24target/riscv: FP extension requirementsTsukasa OI
2022-05-24target/riscv: Change "G" expansionTsukasa OI
2022-05-24target/riscv: Disable "G" by defaultTsukasa OI
2022-05-24target/riscv: Fix coding style on "G" expansionTsukasa OI
2022-05-24target/riscv: Add short-isa-string optionTsukasa OI
2022-05-24target/riscv: Move Zhinx* extensions on ISA stringTsukasa OI
2022-05-24target/riscv: rvv: Fix early exit condition for whole register load/storeeopXD
2022-05-24target/riscv: Fix VS mode hypervisor CSR accessDylan Reid
2022-05-23target/i386: Remove LBREn bit check when access Arch LBR MSRsYang Weijiang
2022-05-19target/arm: Use FIELD definitions for CPACR, CPTR_ELxRichard Henderson
2022-05-19target/arm: Enable FEAT_HCX for -cpu maxRichard Henderson
2022-05-19target/arm: Fix PAuth keys access checks for disabled SEL2Florian Lugou
2022-05-19target/arm: Make number of counters in PMCR follow the CPUPeter Maydell
2022-05-19target/arm/helper.c: Delete stray obsolete commentPeter Maydell
2022-05-19Fix aarch64 debug register names.Chris Howard
2022-05-19hw/intc/arm_gicv3: Use correct number of priority bits for the CPUPeter Maydell
2022-05-19target/arm: Drop unsupported_encoding() macroPeter Maydell
2022-05-19target/arm: Implement FEAT_IDSTPeter Maydell
2022-05-19target/arm: Enable FEAT_S2FWB for -cpu maxPeter Maydell
2022-05-19target/arm: Implement FEAT_S2FWBPeter Maydell
2022-05-19target/arm: Factor out FWB=0 specific part of combine_cacheattrs()Peter Maydell
2022-05-19target/arm: Postpone interpretation of stage 2 descriptor attribute bitsPeter Maydell
2022-05-16Merge tag 'for_upstream' of git://git.kernel.org/pub/scm/virt/kvm/mst/qemu in...Richard Henderson
2022-05-16Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson
2022-05-16target/i386: Fix sanity check on max APIC ID / X2APIC enablementDavid Woodhouse
2022-05-15Merge tag 'or1k-pull-request-20220515' of https://github.com/stffrdhrn/qemu i...Richard Henderson
2022-05-15target/openrisc: Do not reset delay slot flag on early tb exitStafford Horne
2022-05-14target/i386: Support Arch LBR in CPUID enumerationYang Weijiang
2022-05-14target/i386: introduce helper to access supported CPUIDPaolo Bonzini
2022-05-14target/i386: Enable Arch LBR migration states in vmstateYang Weijiang
2022-05-14target/i386: Add MSR access interface for Arch LBRYang Weijiang
2022-05-14target/i386: Add XSAVES support for Arch LBRYang Weijiang
2022-05-14target/i386: Enable support for XSAVES based featuresYang Weijiang
2022-05-14target/i386: Add kvm_get_one_msr helperYang Weijiang
2022-05-14target/i386: Add lbr-fmt vPMU option to support guest LBRYang Weijiang
2022-05-14i386/cpu: Remove the deprecated cpu model 'Icelake-Client'Robert Hoo
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