aboutsummaryrefslogtreecommitdiff
path: root/target
AgeCommit message (Collapse)Author
2020-01-10Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.0-20200108' ↵Peter Maydell
into staging ppc patch queue 2020-01-08 Here's another pull request for qemu-5.0 of ppc related changes. Highlights are: * First parts of support for POWER Secure VMs * Rework to clean up how we pass context information to the various components of the pnv machine (reduces usage of qdev_get_machine()) * Assorted cleanups and bugfixes # gpg: Signature made Wed 08 Jan 2020 05:22:08 GMT # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-5.0-20200108: (26 commits) ppc/pnv: fix check on return value of blk_getlength() ppc/pnv: check return value of blk_pwrite() pnv/psi: Consolidate some duplicated code in pnv_psi_realize() pnv/psi: Add device reset hook pnv/xive: Deduce the PnvXive pointer from XiveTCTX::xptr spapr/xive: Deduce the SpaprXive pointer from XiveTCTX::xptr xive: Add a "presenter" link property to the TCTX object ppc/pnv: Add a "pnor" const link property to the BMC internal simulator ppc/pnv: Add an "nr-threads" property to the base chip class xive: Use the XIVE fabric link under the XIVE router spapr, pnv, xive: Add a "xive-fabric" link to the XIVE router pnv/xive: Use device_class_set_parent_realize() ppc/pnv: Introduce a "xics" property under the POWER8 chip ppc/pnv: Introduce a "xics" property alias under the PSI model spapr/xive: remove redundant check in spapr_match_nvt() ppc/pnv: Drop "num-chips" machine property ppc440_bamboo.c: remove label from bamboo_load_device_tree() spapr.c: remove 'out' label in spapr_dt_cas_updates() ppc/spapr: Don't call KVM_SVM_OFF ioctl on TCG spapr/xive: Use device_class_set_parent_realize() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-10Merge remote-tracking branch ↵Peter Maydell
'remotes/stsquad/tags/pull-testing-and-semihosting-090120-2' into staging Testing fixes and semiconsole support: - build fix (missing x86-iommu stubs) - python fixes for freebsd and OSX - nicer reporting of acceptance failures - fix build nesting of fp-test (breaks bsds) - semihosting clean-ups - support for blocking semihosting console # gpg: Signature made Thu 09 Jan 2020 11:42:51 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-and-semihosting-090120-2: tests/tcg: add user version of dumb-as-bricks semiconsole test tests/tcg: extract __semi_call into a header and expand tests/tcg: add a dumb-as-bricks semihosting console test semihosting: add qemu_semihosting_console_inc for SYS_READC target/arm: only update pc after semihosting completes target/arm: remove unused EXCP_SEMIHOST leg testing: don't nest build for fp-test travis.yml: install homebrew python for OS X travis.yml: duplicate before_script for MacOSX travis.yml: Detach build and test steps travis.yml: avocado: Print logs of non-pass tests only freebsd: use python37 tests/vm: update openbsd to release 6.6 hw/i386/x86-iommu: Add missing stubs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-09semihosting: add qemu_semihosting_console_inc for SYS_READCKeith Packard
Provides a blocking call to read a character from the console using semihosting.chardev, if specified. This takes some careful command line options to use stdio successfully as the serial ports, monitor and semihost all want to use stdio. Here's a sample set of command line options which share stdio between semihost, monitor and serial ports: qemu \ -chardev stdio,mux=on,id=stdio0 \ -serial chardev:stdio0 \ -semihosting-config enable=on,chardev=stdio0 \ -mon chardev=stdio0,mode=readline This creates a chardev hooked to stdio and then connects all of the subsystems to it. A shorter mechanism would be good to hear about. Signed-off-by: Keith Packard <keithp@keithp.com> Message-Id: <20191104204230.12249-1-keithp@keithp.com> [AJB: fixed up deadlock, minor commit title reword] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Keith Packard <keithp@keithp.com> Tested-by: Keith Packard <keithp@keithp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-01-09target/arm: only update pc after semihosting completesAlex Bennée
Before we introduce blocking semihosting calls we need to ensure we can restart the system on semi hosting exception. To be able to do this the EXCP_SEMIHOST operation should be idempotent until it finally completes. Practically this means ensureing we only update the pc after the semihosting call has completed. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Keith Packard <keithp@keithp.com> Tested-by: Keith Packard <keithp@keithp.com>
2020-01-09target/arm: remove unused EXCP_SEMIHOST legAlex Bennée
All semihosting exceptions are dealt with earlier in the common code so we should never get here. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Keith Packard <keithp@keithp.com> Tested-by: Keith Packard <keithp@keithp.com>
2020-01-08ppc/spapr: Don't call KVM_SVM_OFF ioctl on TCGBharata B Rao
Invoking KVM_SVM_OFF ioctl for TCG guests will lead to a QEMU crash. Fix this by ensuring that we don't call KVM_SVM_OFF ioctl on TCG. Reported-by: Alexey Kardashevskiy <aik@ozlabs.ru> Fixes: 4930c1966249 ("ppc/spapr: Support reboot of secure pseries guest") Signed-off-by: Bharata B Rao <bharata@linux.ibm.com> Message-Id: <20200102054155.13175-1-bharata@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08ppc/spapr: Support reboot of secure pseries guestBharata B Rao
A pseries guest can be run as a secure guest on Ultravisor-enabled POWER platforms. When such a secure guest is reset, we need to release/reset a few resources both on ultravisor and hypervisor side. This is achieved by invoking this new ioctl KVM_PPC_SVM_OFF from the machine reset path. As part of this ioctl, the secure guest is essentially transitioned back to normal mode so that it can reboot like a regular guest and become secure again. This ioctl has no effect when invoked for a normal guest. If this ioctl fails for a secure guest, the guest is terminated. Signed-off-by: Bharata B Rao <bharata@linux.ibm.com> Message-Id: <20191219031445.8949-3-bharata@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08target/ppc: Handle AIL=0 in ppc_excp_vector_offsetFabiano Rosas
The exception vector offset calculation was moved into a function but the case when AIL=0 was not checked. The reason we got away with this is that the sole caller of ppc_excp_vector_offset checks the AIL before calling the function: /* Handle AIL */ if (ail) { ... vector |= ppc_excp_vector_offset(cs, ail); } Fixes: 2586a4d7a0 ("target/ppc: Move exception vector offset computation into a function") Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20191217142512.574075-1-farosas@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08target/ppc: Remove unused PPC_INPUT_INT definesFabiano Rosas
They were added in "16415335be Use correct input constant" with a single use in kvm_arch_pre_run but that function's implementation was removed by "1e8f51e856 ppc: remove idle_timer logic". Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20191218014616.686124-1-farosas@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-07Merge remote-tracking branch 'remotes/elmarco/tags/prop-ptr-pull-request' ↵Peter Maydell
into staging Clean-ups: qom-ify serial and remove QDEV_PROP_PTR Hi, QDEV_PROP_PTR is marked in multiple places as "FIXME/TODO/remove me". In most cases, it can be easily replaced with QDEV_PROP_LINK when the pointer points to an Object. There are a few places where such substitution isn't possible. For those places, it seems reasonable to use a specific setter method instead, and keep the user_creatable = false. In other places, proper usage of qdev or other facilies is the solution. The serial code wasn't converted to qdev, which makes it a bit more archaic to deal with. Let's convert it first, so we can more easily embed it from other devices, and re-export some properties and drop QDEV_PROP_PTR usage. # gpg: Signature made Tue 07 Jan 2020 15:01:26 GMT # gpg: using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5 # gpg: issuer "marcandre.lureau@redhat.com" # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full] # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full] # Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5 * remotes/elmarco/tags/prop-ptr-pull-request: (37 commits) qdev/qom: remove some TODO limitations now that PROP_PTR is gone qdev: remove QDEV_PROP_PTR qdev: remove PROP_MEMORY_REGION omap-gpio: remove PROP_PTR omap-i2c: remove PROP_PTR omap-intc: remove PROP_PTR smbus-eeprom: remove PROP_PTR cris: improve passing PIC interrupt vector to the CPU mips/cps: fix setting saar property qdev: use g_strcmp0() instead of open-coding it leon3: use qdev gpio facilities for the PIL leon3: use qemu_irq framework instead of callback as property dp8393x: replace PROP_PTR with PROP_LINK etraxfs: remove PROP_PTR usage lance: replace PROP_PTR with PROP_LINK vmmouse: replace PROP_PTR with PROP_LINK sm501: make SerialMM a child, export chardev property mips: use sysbus_mmio_get_region() instead of internal fields mips: use sysbus_add_io() mips: baudbase is 115200 by default ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-07cris: improve passing PIC interrupt vector to the CPUMarc-André Lureau
Instead of accessing cpu interrupt vector directly from PIC, send the vector value over the qemu_irq. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2020-01-07leon3: use qdev gpio facilities for the PILMarc-André Lureau
As Peter Maydell once said: "Creating a gpio pin on some object that isn't yourself looks a bit odd, but all this leon3 code is modifying the CPU object from the outside anyway. Someday we might tidy it up, but not today." Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2020-01-07leon3: use qemu_irq framework instead of callback as propertyMarc-André Lureau
"set_pin_in" property is used to define a callback mechanism where the device says "call the callback function, passing it an opaque cookie and a 32-bit value". We already have a generic mechanism for doing that, which is the qemu_irq. So we should just use that. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com>
2020-01-07target/m68k: only change valid bits in CACRLaurent Vivier
This is used by netBSD (and MacOS ROM) to detect the MMU type Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Message-Id: <20191220172415.35838-1-laurent@vivier.eu> [lv: add a comment before m680x0_cpu_common()] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-01-06target/xtensa: use MPU background map from core configurationMax Filippov
Configuration overlay may define MPU background map. Import core-matmap.h from the overlay and use XCHAL_MPU_BACKGROUND_MAP macro if it's defined. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-01-06target/xtensa: import xtensa/config/core-isa.hMax Filippov
Import core-isa.h from its canonical place in the configuration overlay. Drop --xform option from the tar command line. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-01-06target/xtensa: fix ps.ring use in MPU configsMax Filippov
Allow ps.ring modification by wsr.ps/xsr.ps and use ps.ring value in xtensa_get_[c]ring on configurations with MPU. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-01-06Merge remote-tracking branch ↵Peter Maydell
'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging x86 and machine queue, 2019-12-20 Bug fix: * Resolve CPU models to v1 by default (Eduardo Habkost) Cleanup: * Remove incorrect numa_mem_supported checks (Igor Mammedov) # gpg: Signature made Fri 20 Dec 2019 19:19:02 GMT # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-and-machine-pull-request: numa: properly check if numa is supported numa: remove not needed check i386: Resolve CPU models to v1 by default Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-03Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20191220' into staging target-arm queue: * Support emulating the generic timers at frequencies other than 62.5MHz * Various fixes for SMMUv3 emulation bugs * Improve assert error message for hflags mismatches * arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on() # gpg: Signature made Fri 20 Dec 2019 14:25:51 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20191220: arm/arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on() target/arm: Display helpful message when hflags mismatch hw/arm/smmuv3: Report F_STE_FETCH fault address in correct word position hw/arm/smmuv3: Use correct bit positions in EVT_SET_ADDR2 macro hw/arm/smmuv3: Align stream table base address to table size hw/arm/smmuv3: Check stream IDs against actual table LOG2SIZE hw/arm/smmuv3: Correct SMMU_BASE_ADDR_MASK value hw/arm/smmuv3: Apply address mask to linear strtab base address ast2600: Configure CNTFRQ at 1125MHz target/arm: Prepare generic timer for per-platform CNTFRQ target/arm: Abstract the generic timer frequency target/arm: Remove redundant scaling of nexttick Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-20Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20191219' into stagingPeter Maydell
More s390x patches: - tcg: implement LOAD/STORE TO REAL ADDRESS inline - fixes in tests, the bios, and diag308 handling # gpg: Signature made Thu 19 Dec 2019 10:53:19 GMT # gpg: using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF # gpg: issuer "cohuck@redhat.com" # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown] # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full] # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full] # gpg: aka "Cornelia Huck <cohuck@kernel.org>" [unknown] # gpg: aka "Cornelia Huck <cohuck@redhat.com>" [unknown] # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20191219: s390x: Properly fetch and test the short psw on diag308 subc 0/1 pc-bios/s390: Update firmware images pc-bios/s390x: Fix reset psw mask tests/boot-sector: Fix the bad s390x assembler code target/s390x: Implement LOAD/STORE TO REAL ADDRESS inline target/s390x: Split out helper_per_store_real Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-20arm/arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on()Niek Linnenbank
After setting CP15 bits in arm_set_cpu_on() the cached hflags must be rebuild to reflect the changed processor state. Without rebuilding, the cached hflags would be inconsistent until the next call to arm_rebuild_hflags(). When QEMU is compiled with debugging enabled (--enable-debug), this problem is captured shortly after the first call to arm_set_cpu_on() for CPUs running in ARM 32-bit non-secure mode: qemu-system-arm: target/arm/helper.c:11359: cpu_get_tb_cpu_state: Assertion `flags == rebuild_hflags_internal(env)' failed. Aborted (core dumped) Fixes: 0c7f8c43daf65 Cc: qemu-stable@nongnu.org Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-20target/arm: Display helpful message when hflags mismatchPhilippe Mathieu-Daudé
Instead of crashing in a confuse way, give some hint to the user about why we aborted. He might report the issue without having to use a debugger. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20191209134552.27733-1-philmd@redhat.com Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-20target/arm: Prepare generic timer for per-platform CNTFRQAndrew Jeffery
The ASPEED AST2600 clocks the generic timer at the rate of HPLL. On recent firmwares this is at 1125MHz, which is considerably quicker than the assumed 62.5MHz of the current generic timer implementation. The delta between the value as read from CNTFRQ and the true rate of the underlying QEMUTimer leads to sticky behaviour in AST2600 guests. Add a feature-gated property exposing CNTFRQ for ARM CPUs providing the generic timer. This allows platforms to configure CNTFRQ (and the associated QEMUTimer) to the appropriate frequency prior to starting the guest. As the platform can now determine the rate of CNTFRQ we're exposed to limitations of QEMUTimer that didn't previously materialise: In the course of emulation we need to arbitrarily and accurately convert between guest ticks and time, but we're constrained by QEMUTimer's use of an integer scaling factor. The effect is QEMUTimer cannot exactly capture the period of frequencies that do not cleanly divide NANOSECONDS_PER_SECOND for scaling ticks to time. As such, provide an equally inaccurate scaling factor for scaling time to ticks so at least a self-consistent inverse relationship holds. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: a22db9325f96e39f76e3c2baddcb712149f46bf2.1576215453.git-series.andrew@aj.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-20target/arm: Abstract the generic timer frequencyAndrew Jeffery
Prepare for SoCs such as the ASPEED AST2600 whose firmware configures CNTFRQ to values significantly larger than the static 62.5MHz value currently derived from GTIMER_SCALE. As the OS potentially derives its timer periods from the CNTFRQ value the lack of support for running QEMUTimers at the appropriate rate leads to sticky behaviour in the guest. Substitute the GTIMER_SCALE constant with use of a helper to derive the period from gt_cntfrq_hz stored in struct ARMCPU. Initially set gt_cntfrq_hz to the frequency associated with GTIMER_SCALE so current behaviour is maintained. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 40bd8df043f66e1ccfb3e9482999d099ac72bb2e.1576215453.git-series.andrew@aj.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-20target/arm: Remove redundant scaling of nexttickAndrew Jeffery
The corner-case codepath was adjusting nexttick such that overflow wouldn't occur when timer_mod() scaled the value back up. Remove a use of GTIMER_SCALE and avoid unnecessary operations by calling timer_mod_ns() directly. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-id: f8c680720e3abe55476e6d9cb604ad27fdbeb2e0.1576215453.git-series.andrew@aj.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-20Merge remote-tracking branch ↵Peter Maydell
'remotes/stsquad/tags/pull-tesing-and-misc-191219-1' into staging Various testing and logging updates - test tci with Travis - enable multiarch testing in Travis - default to out-of-tree builds - make changing logfile safe via RCU - remove redundant tests - remove gtester test from docker - convert DEBUG_MMAP to tracepoints - remove hand rolled glob function - trigger tcg re-configure when needed # gpg: Signature made Thu 19 Dec 2019 08:24:08 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-tesing-and-misc-191219-1: (25 commits) tests/tcg: ensure we re-configure if configure.sh is updated trace: replace hand-crafted pattern_glob with g_pattern_match_simple linux-user: convert target_munmap debug to a tracepoint linux-user: log page table changes under -d page linux-user: add target_mmap_complete tracepoint linux-user: convert target_mmap debug to tracepoint linux-user: convert target_mprotect debug to tracepoint travis.yml: Remove the redundant clang-with-MAIN_SOFTMMU_TARGETS entry docker: gtester is no longer used Added tests for close and change of logfile. Add use of RCU for qemu_logfile. qemu_log_lock/unlock now preserves the qemu_logfile handle. Add a mutex to guarantee single writer to qemu_logfile handle. Cleaned up flow of code in qemu_set_log(), to simplify and clarify. Fix double free issue in qemu_set_log_filename(). ci: build out-of-tree travis.yml: Enable builds on arm64, ppc64le and s390x tests/test-util-filemonitor: Skip test on non-x86 Travis containers tests/hd-geo-test: Skip test when images can not be created iotests: Skip test 079 if it is not possible to create large files ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-20Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier2/tags/trivial-branch-pull-request' into staging Trivial fixes (20191218) # gpg: Signature made Wed 18 Dec 2019 13:00:34 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-pull-request: qemu-doc: Remove the unused "Guest Agent" node Revert "qemu-options.hx: Update for reboot-timeout parameter" target/sparc: Remove old TODO file test-keyval: Tighten test of trailing crap after size util/cutils: Turn FIXME comment into QEMU_BUILD_BUG_ON() monitor: Remove unused define MAINTAINERS: Add hw/sd/ssi-sd.c in the SD section Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-20Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* More uses of RCU_READ_LOCK_GUARD (Dave, myself) * QOM doc improvments (Greg) * Cleanups from the Meson conversion (Marc-André) * Support for multiple -accel options (myself) * Many x86 machine cleanup (Philippe, myself) * tests/migration-test cleanup (Juan) * PC machine removal and next round of deprecation (Thomas) * kernel-doc integration (Peter, myself) # gpg: Signature made Wed 18 Dec 2019 01:35:02 GMT # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (87 commits) vga: cleanup mapping of VRAM for non-PCI VGA hw/display: Remove "rombar" hack from vga-pci and vmware_vga hw/pci: Remove the "command_serr_enable" property hw/audio: Remove the "use_broken_id" hack from the AC97 device hw/i386: Remove the deprecated machines 0.12 up to 0.15 hw/pci-host: Add Kconfig entry to select the IGD Passthrough Host Bridge hw/pci-host/i440fx: Extract the IGD passthrough host bridge device hw/pci-host/i440fx: Use definitions instead of magic values hw/pci-host/i440fx: Use size_t to iterate over ARRAY_SIZE() hw/pci-host/i440fx: Extract PCII440FXState to "hw/pci-host/i440fx.h" hw/pci-host/i440fx: Correct the header description Fix some comment spelling errors. target/i386: remove unused pci-assign codes WHPX: refactor load library migration: check length directly to make sure the range is aligned memory: include MemoryListener documentation and some missing function parameters docs: add memory API reference memory.h: Silence kernel-doc complaints docs: Create bitops.rst as example of kernel-docs bitops.h: Silence kernel-doc complaints ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-19i386: Resolve CPU models to v1 by defaultEduardo Habkost
When using `query-cpu-definitions` using `-machine none`, QEMU is resolving all CPU models to their latest versions. The actual CPU model version being used by another machine type (e.g. `pc-q35-4.0`) might be different. In theory, this was OK because the correct CPU model version is returned when using the correct `-machine` argument. Except that in practice, this breaks libvirt expectations: libvirt always use `-machine none` when checking if a CPU model is runnable, because runnability is not expected to be affected when the machine type is changed. For example, when running on a Haswell host without TSX, Haswell-v4 is runnable, but Haswell-v1 is not. On those hosts, `query-cpu-definitions` says Haswell is runnable if using `-machine none`, but Haswell is actually not runnable using any of the `pc-*` machine types (because they resolve Haswell to Haswell-v1). In other words, we're breaking the "runnability guarantee" we promised to not break for a few releases (see qemu-deprecated.texi). To address this issue, change the default CPU model version to v1 on all machine types, so we make `query-cpu-definitions` output when using `-machine none` match the results when using `pc-*`. This will change in the future (the plan is to always return the latest CPU model version if using `-machine none`), but only after giving libvirt the opportunity to adapt. Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1779078 Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20191205223339.764534-1-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-12-18qemu_log_lock/unlock now preserves the qemu_logfile handle.Robert Foley
qemu_log_lock() now returns a handle and qemu_log_unlock() receives a handle to unlock. This allows for changing the handle during logging and ensures the lock() and unlock() are for the same file. Also in target/tilegx/translate.c removed the qemu_log_lock()/unlock() calls (and the log("\n")), since the translator can longjmp out of the loop if it attempts to translate an instruction in an inaccessible page. Signed-off-by: Robert Foley <robert.foley@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20191118211528.3221-5-robert.foley@linaro.org>
2019-12-18s390x: Properly fetch and test the short psw on diag308 subc 0/1Janosch Frank
We need to actually fetch the cpu mask and set it. As we invert the short psw indication in the mask, SIE will report a specification exception, if it wasn't present in the reset psw. Signed-off-by: Janosch Frank <frankja@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20191129142025.21453-2-frankja@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-12-18target/s390x: Implement LOAD/STORE TO REAL ADDRESS inlineRichard Henderson
These are trivially done by performing a memory operation with the correct mmu_idx. The only tricky part is using get_address directly in order to get the address wrapped; we cannot use la2 because of the format. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20191211203614.15611-3-richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-12-18target/s390x: Split out helper_per_store_realRichard Henderson
Split the PER handling for store-to-real-address into its own helper function, conditionally called when PER is enabled, just as we do for per_branch and per_ifetch. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20191211203614.15611-2-richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-12-18target/sparc: Remove old TODO fileThomas Huth
This file hasn't seen a real (non-trivial) update since 2008 anymore, so we can assume that it is pretty much out of date and nobody cares for it anymore. Let's simply remove it. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com> Message-Id: <20190930171044.25312-1-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-12-18ppc: make Error **errp const where it is appropriateVladimir Sementsov-Ogievskiy
Mostly, Error ** is for returning error from the function, so the callee sets it. However kvmppc_hint_smt_possible gets already filled errp parameter. It doesn't change the pointer itself, only change the internal state of referenced Error object. So we can make it Error *const * errp, to stress the behavior. It will also help coccinelle script (in future) to distinguish such cases from common errp usage. While there, rename the function to kvmppc_error_append_smt_possible_hint(). Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <20191205174635.18758-8-vsementsov@virtuozzo.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Markus Armbruster <armbru@redhat.com> [Commit message replaced] Signed-off-by: Markus Armbruster <armbru@redhat.com>
2019-12-18Revert "ppc: well form kvmppc_hint_smt_possible error hint helper"Markus Armbruster
This reverts commit cdcca22aabafc0496894ce05c80097684832c7d9. Commit cdcca22aaba is a superseded version of the next commit that crept in by accident. Revert it, so the final version applies. Signed-off-by: Markus Armbruster <armbru@redhat.com>
2019-12-18Fix some comment spelling errors.Cameron Esfahani
Signed-off-by: Cameron Esfahani <dirty@apple.com> Message-Id: <086c197db928384b8697edfa64755e2cb46c8100.1575685843.git.dirty@apple.com> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-12-18target/i386: remove unused pci-assign codesEiichi Tsukata
Legacy PCI device assignment has been already removed in commit ab37bfc7d641 ("pci-assign: Remove"), but some codes remain unused. CC: qemu-trivial@nongnu.org Signed-off-by: Eiichi Tsukata <devel@etsukata.com> Message-Id: <20191209072932.313056-1-devel@etsukata.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-12-18WHPX: refactor load librarySunil Muthuswamy
This refactors the load library of WHV libraries to make it more modular. It makes a helper routine that can be called on demand. This allows future expansion of load library/functions to support functionality that is dependent on some feature being available. Signed-off-by: Sunil Muthuswamy <sunilmut@microsoft.com> Message-Id: <MW2PR2101MB1116578040BE1F0C1B662318C0760@MW2PR2101MB1116.namprd21.prod.outlook.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-12-17x86: move more x86-generic functions out of PC filesPaolo Bonzini
These are needed by microvm too, so move them outside of PC-specific files. With this patch, microvm.c need not include pc.h anymore. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-12-17x86: move SMM property to X86MachineStatePaolo Bonzini
Add it to microvm as well, it is a generic property of the x86 architecture. Suggested-by: Sergio Lopez <slp@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-12-17hw: replace hw/i386/pc.h with a header just for the i8259Paolo Bonzini
Remove the need to include i386/pc.h to get to the i8259 functions. This is enough to remove the inclusion of hw/i386/pc.h from all non-x86 files. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-12-17kvm: introduce kvm_kernel_irqchip_* functionsPaolo Bonzini
The KVMState struct is opaque, so provide accessors for the fields that will be moved from current_machine to the accelerator. For now they just forward to the machine object, but this will change. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-12-17kvm: convert "-machine kvm_shadow_mem" to an accelerator propertyPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-12-17qom: add object_new_with_classPaolo Bonzini
Similar to CPU and machine classes, "-accel" class names are mangled, so we have to first get a class via accel_find and then instantiate it. Provide a new function to instantiate a class without going through object_class_get_name, and use it for CPUs and machines already. Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-12-17Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.0-20191217' ↵Peter Maydell
into staging ppc patch queue 2019-12-17 This is the first pull request for the qemu-5.0 branch. It has a lot of accumulated changes, including: * SLOF update to support boot using the IOMMU (will become necessary for secure guests) * Clean ups to pnv handling of chip models * A number of extensions to the powernv machine model * TCG extensions to allow powernv emulated systems to run KVM guests * Outline support for POWER10 chips in powernv * Cleanups to the ibm,client-architecture-support feature negotiation path * XIVE reworks to better handle the powernv machine * Improvements to not waste interrupt queues and other semi-scarce resources when using XIVE under KVM # gpg: Signature made Tue 17 Dec 2019 04:42:20 GMT # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-5.0-20191217: (88 commits) pseries: Update SLOF firmware image ppc/pnv: Drop PnvChipClass::type ppc/pnv: Introduce PnvChipClass::xscom_pcba() method ppc/pnv: Drop pnv_chip_is_power9() and pnv_chip_is_power10() helpers ppc/pnv: Pass content of the "compatible" property to pnv_dt_xscom() ppc/pnv: Pass XSCOM base address and address size to pnv_dt_xscom() ppc/pnv: Introduce PnvChipClass::xscom_core_base() method ppc/pnv: Introduce PnvChipClass::intc_print_info() method ppc/pnv: Drop pnv_is_power9() and pnv_is_power10() helpers ppc/pnv: Introduce PnvMachineClass::dt_power_mgt() ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compat ppc/pnv: Drop PnvPsiClass::chip_type ppc/pnv: Introduce PnvPsiClass::compat ppc: Drop useless extern annotation for functions ppc/pnv: Fix OCC common area region mapping ppc/pnv: Introduce PBA registers ppc/pnv: Make PnvXScomInterface an incomplete type ppc/pnv: populate the DT with realized XSCOM devices ppc/pnv: Loop on the whole hierarchy to populate the DT with the XSCOM nodes target/ppc: Add SPR TBU40 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-17Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' ↵Peter Maydell
into staging x86 queue, 2019-12-16 Feature: * Cooperlake CPU model Cleanups: * Use g_autofree in a few places # gpg: Signature made Mon 16 Dec 2019 19:36:51 GMT # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-next-pull-request: i386: Use g_autofree in a few places i386: Add new CPU model Cooperlake i386: Add macro for stibp i386: Add MSR feature bit for MDS-NO Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-17target/ppc: Add SPR TBU40Suraj Jitindar Singh
The spr TBU40 is used to set the upper 40 bits of the timebase register, present on POWER5+ and later processors. This register can only be written by the hypervisor, and cannot be read. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191128134700.16091-5-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17target/ppc: Add SPR ASDRSuraj Jitindar Singh
The Access Segment Descriptor Register (ASDR) provides information about the storage element when taking a hypervisor storage interrupt. When performing nested radix address translation, this is normally the guest real address. This register is present on POWER9 processors and later. Implement the ADSR, note read and write access is limited to the hypervisor. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191128134700.16091-4-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17target/ppc: Work [S]PURR implementation and add HV supportSuraj Jitindar Singh
The Processor Utilisation of Resources Register (PURR) and Scaled Processor Utilisation of Resources Register (SPURR) provide an estimate of the resources used by the thread, present on POWER7 and later processors. Currently the [S]PURR registers simply count at the rate of the timebase. Preserve this behaviour but rework the implementation to store an offset like the timebase rather than doing the calculation manually. Also allow hypervisor write access to the register along with the currently available read access. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ clg: rebased on current ppc tree ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191128134700.16091-3-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-01 19:53:00 +0000