aboutsummaryrefslogtreecommitdiff
path: root/target
AgeCommit message (Expand)Author
2018-11-08target/ppc: add external PID supportRoman Kapl
2018-11-06target/i386: Clear RF on SYSCALL instructionRudolf Marek
2018-11-06x86: hv_evmcs CPU flag supportVitaly Kuznetsov
2018-11-06target/arm: Fix ATS1Hx instructionsPeter Maydell
2018-11-06target/arm: Set S and PTW in 64-bit PAR formatPeter Maydell
2018-11-06target/arm: Remove can't-happen if() from handle_vec_simd_shli()Peter Maydell
2018-11-02target/arm: Conditionalize some asserts on aarch32 supportRichard Henderson
2018-11-02Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf1' in...Peter Maydell
2018-11-02Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-3.1-pull-request' ...Peter Maydell
2018-11-01Merge remote-tracking branch 'remotes/rth/tags/pull-dt-20181031' into stagingPeter Maydell
2018-11-01target/m68k: use EXCP_ILLEGAL instead of EXCP_UNSUPPORTEDLaurent Vivier
2018-10-31decodetree: Remove "insn" argument from trans_* expandersRichard Henderson
2018-10-30i386: Add PKU on Skylake-Server CPU modelTao Xu
2018-10-30i386: Add new model of Cascadelake-ServerTao Xu
2018-10-30x86: define a new MSR based feature word -- FEATURE_WORDS_ARCH_CAPABILITIESRobert Hoo
2018-10-30x86: Data structure changes to support MSR based featuresRobert Hoo
2018-10-30kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS system ioctlRobert Hoo
2018-10-30target/i386: Remove #ifdeffed-out icebp debugging hackPeter Maydell
2018-10-30i386: correct cpu_x86_cpuid(0xd)Sebastian Andrzej Siewior
2018-10-30target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64Dayeol Lee
2018-10-29target/mips: Amend MXU ASE overview noteAleksandar Markovic
2018-10-29target/mips: Move MXU_EN check one level higherAleksandar Markovic
2018-10-29target/mips: Add emulation of MXU instructions S32LDD and S32LDDRCraig Janeczek
2018-10-29target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSUCraig Janeczek
2018-10-29target/mips: Add emulation of MXU instruction D16MACCraig Janeczek
2018-10-29target/mips: Add emulation of MXU instruction D16MULCraig Janeczek
2018-10-29target/mips: Add emulation of MXU instruction S8LDDCraig Janeczek
2018-10-29target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switchAleksandar Markovic
2018-10-29target/mips: Add emulation of MXU instructions S32I2M and S32M2ICraig Janeczek
2018-10-29target/mips: Add emulation of non-MXU MULL within MXU decoding engineCraig Janeczek
2018-10-29target/mips: Add bit encoding for MXU operand getting pattern 'optn3'Craig Janeczek
2018-10-29target/mips: Add bit encoding for MXU operand getting pattern 'optn2'Craig Janeczek
2018-10-29target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2'Aleksandar Markovic
2018-10-29target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2'Craig Janeczek
2018-10-29target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1'Aleksandar Markovic
2018-10-29target/mips: Add MXU decoding engineAleksandar Markovic
2018-10-29target/mips: Add and integrate MXU decoding engine placeholderAleksandar Markovic
2018-10-29target/mips: Amend MXU instruction opcodesAleksandar Markovic
2018-10-29target/mips: Define a bit for MXU in insn_flagsCraig Janeczek
2018-10-29target/mips: Introduce MXU registersCraig Janeczek
2018-10-29target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder casesAleksandar Markovic
2018-10-25target/mips: Add disassembler support for nanoMIPSAleksandar Markovic
2018-10-25target/mips: Implement emulation of nanoMIPS EVA instructionsDimitrije Nikolic
2018-10-25target/mips: Add nanoMIPS CRC32 instruction poolAleksandar Markovic
2018-10-25Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf0' in...Peter Maydell
2018-10-24Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-oct-2018-part...Peter Maydell
2018-10-24target/mips: Fix decoding of ALIGN and DALIGN instructionsAleksandar Markovic
2018-10-24target/mips: Fix the title of translate.cAleksandar Markovic
2018-10-24target/mips: Define the R5900 CPUFredrik Noring
2018-10-24target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user onlyFredrik Noring