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AgeCommit message (Expand)Author
2022-01-11target/mips: Extract trap code into env->error_codeRichard Henderson
2022-01-11target/mips: Extract break code into env->error_codeRichard Henderson
2022-01-09target/m68k: don't word align SP in stack frame if M68K_FEATURE_UNALIGNED_DAT...Mark Cave-Ayland
2022-01-08target/riscv: Implement the stval/mtval illegal instructionAlistair Francis
2022-01-08target/riscv: Fixup setting GVAAlistair Francis
2022-01-08target/riscv: Set the opcode in DisasContextAlistair Francis
2022-01-08target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot
2022-01-08target/riscv: modification of the trans_csrxx for 128-bit supportFrédéric Pétrot
2022-01-08target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot
2022-01-08target/riscv: adding high part of some csrsFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit M extensionFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit shift instructionsFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit U-type instructionsFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit bitwise instructionsFrédéric Pétrot
2022-01-08target/riscv: accessors to registers upper part and 128-bit load/storeFrédéric Pétrot
2022-01-08target/riscv: moving some insns close to similar insnsFrédéric Pétrot
2022-01-08target/riscv: setup everything for rv64 to support rv128 executionFrédéric Pétrot
2022-01-08target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot
2022-01-08target/riscv: separation of bitwise logic and arithmetic helpersFrédéric Pétrot
2022-01-08target/riscv: additional macros to check instruction supportFrédéric Pétrot
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot
2022-01-08target/riscv: Fix position of 'experimental' commentPhilipp Tomsich
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing ...Frank Chang
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang
2022-01-08target/riscv: Enable the Hypervisor extension by defaultAlistair Francis
2022-01-08target/riscv: Mark the Hypervisor extension as non experimentalAlistair Francis
2022-01-08target/riscv/pmp: fix no pmp illegal intrsNikita Shubin
2022-01-07target/arm: Add missing FEAT_TLBIOS instructionsIdan Horowitz
2022-01-06linux-user/nios2: Map a real kuser pageRichard Henderson
2022-01-06linux-user/nios2: Properly emulate EXCP_TRAPRichard Henderson
2022-01-06target/sh4: Implement prctl_unalign_sigbusRichard Henderson
2022-01-06target/hppa: Implement prctl_unalign_sigbusRichard Henderson
2022-01-06target/alpha: Implement prctl_unalign_sigbusRichard Henderson
2022-01-04target/ppc: do not call hreg_compute_hflags() in helper_store_mmcr0()Daniel Henrique Barboza
2022-01-04target/ppc: Use env->pnc_cyc_cntRichard Henderson
2022-01-04target/ppc: Rewrite pmu_increment_insnsRichard Henderson
2022-01-04target/ppc: Cache per-pmc insn and cycle count settingsRichard Henderson
2022-01-04target/ppc: powerpc_excp: Stop passing excp_model aroundFabiano Rosas
2022-01-04target/ppc: powerpc_excp: Move system call vectored code togetherFabiano Rosas
2022-01-04target/ppc: powerpc_excp: Set vector earlierFabiano Rosas
2022-01-04target/ppc: powerpc_excp: Add excp_vectors bounds checkFabiano Rosas
2022-01-04target/ppc: powerpc_excp: Set alternate SRRs directlyFabiano Rosas
2022-01-04target/ppc: do not silence snan in xscvspdpnMatheus Ferst
2022-01-04ppc/ppc405: Dump specific registersCédric Le Goater
2022-01-04ppc/ppc405: Introduce a store helper for SPR_40x_PIDCédric Le Goater
2022-01-04ppc/ppc405: Restore TCR and STR write handlersCédric Le Goater
2022-01-04ppc/ppc405: Activate MMU logsCédric Le Goater
2022-01-04target/ppc: Print out literal exception names in logsCédric Le Goater