| Age | Commit message (Expand) | Author |
|---|
| 2024-01-10 | target/riscv/kvm: add RISCV_CONFIG_REG() | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/kvm: change timer regs size to u64 | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64 | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32 | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/cpu.c: fix machine IDs getters | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/pmp: Use hwaddr instead of target_ulong for RV32 | Ivan Klokov |
| 2024-01-10 | target/riscv: Not allow write mstatus_vs without RVV | LIU Zhiwei |
| 2024-01-10 | target/riscv: Fix th.dcache.cval1 priviledge check | LIU Zhiwei |
| 2024-01-10 | target/riscv: The whole vector register move instructions depend on vsew | Max Chou |
| 2024-01-10 | target/riscv: Add vill check for whole vector register move instructions | Max Chou |
| 2024-01-09 | target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs | Peter Maydell |
| 2024-01-09 | target/arm: Enhance CPU_LOG_INT to show SPSR on AArch64 exception-entry | Peter Maydell |
| 2024-01-09 | target/arm: Report HCR_EL2.{NV,NV1,NV2} in cpu dumps | Peter Maydell |
| 2024-01-09 | target/arm: Mark up VNCR offsets (offsets >= 0x200, except GIC) | Peter Maydell |
| 2024-01-09 | target/arm: Mark up VNCR offsets (offsets 0x168..0x1f8) | Peter Maydell |
| 2024-01-09 | target/arm: Mark up VNCR offsets (offsets 0x100..0x160) | Peter Maydell |
| 2024-01-09 | target/arm: Mark up VNCR offsets (offsets 0x0..0xff) | Peter Maydell |
| 2024-01-09 | target/arm: Report VNCR_EL2 based faults correctly | Peter Maydell |
| 2024-01-09 | target/arm: Implement FEAT_NV2 redirection of sysregs to RAM | Peter Maydell |
| 2024-01-09 | target/arm: Handle FEAT_NV2 redirection of SPSR_EL2, ELR_EL2, ESR_EL2, FAR_EL2 | Peter Maydell |
| 2024-01-09 | target/arm: Handle FEAT_NV2 changes to when SPSR_EL1.M reports EL2 | Peter Maydell |
| 2024-01-09 | target/arm: Implement VNCR_EL2 register | Peter Maydell |
| 2024-01-09 | target/arm: Handle HCR_EL2 accesses for FEAT_NV2 bits | Peter Maydell |
| 2024-01-09 | target/arm: Add FEAT_NV to max, neoverse-n2, neoverse-v1 CPUs | Peter Maydell |
| 2024-01-09 | target/arm: Handle FEAT_NV page table attribute changes | Peter Maydell |
| 2024-01-09 | target/arm: Treat LDTR* and STTR* as LDR/STR when NV, NV1 is 1, 1 | Peter Maydell |
| 2024-01-09 | target/arm: Don't honour PSTATE.PAN when HCR_EL2.{NV, NV1} == {1, 1} | Peter Maydell |
| 2024-01-09 | target/arm: Always use arm_pan_enabled() when checking if PAN is enabled | Peter Maydell |
| 2024-01-09 | target/arm: Trap registers when HCR_EL2.{NV, NV1} == {1, 1} | Peter Maydell |
| 2024-01-09 | target/arm: Set SPSR_EL1.M correctly when nested virt is enabled | Peter Maydell |
| 2024-01-09 | target/arm: Make NV reads of CurrentEL return EL2 | Peter Maydell |
| 2024-01-09 | target/arm: Trap sysreg accesses for FEAT_NV | Peter Maydell |
| 2024-01-09 | target/arm: Move FPU/SVE/SME access checks up above ARM_CP_SPECIAL_MASK check | Peter Maydell |
| 2024-01-09 | target/arm: Make EL2 cpreg accessfns safe for FEAT_NV EL1 accesses | Peter Maydell |
| 2024-01-09 | target/arm: *_EL12 registers should UNDEF when HCR_EL2.E2H is 0 | Peter Maydell |
| 2024-01-09 | target/arm: Record correct opcode fields in cpreg for E2H aliases | Peter Maydell |
| 2024-01-09 | target/arm: Allow use of upper 32 bits of TBFLAG_A64 | Peter Maydell |
| 2024-01-09 | target/arm: Always honour HCR_EL2.TSC when HCR_EL2.NV is set | Peter Maydell |
| 2024-01-09 | target/arm: Enable trapping of ERET for FEAT_NV | Peter Maydell |
| 2024-01-09 | target/arm: Implement HCR_EL2.AT handling | Peter Maydell |
| 2024-01-09 | target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NV | Peter Maydell |
| 2024-01-09 | target/arm: Set CTR_EL0.{IDC,DIC} for the 'max' CPU | Peter Maydell |
| 2024-01-08 | Replace "iothread lock" with "BQL" in comments | Stefan Hajnoczi |
| 2024-01-08 | qemu/main-loop: rename qemu_cond_wait_iothread() to qemu_cond_wait_bql() | Stefan Hajnoczi |
| 2024-01-08 | qemu/main-loop: rename QEMU_IOTHREAD_LOCK_GUARD to BQL_LOCK_GUARD | Stefan Hajnoczi |
| 2024-01-08 | system/cpus: rename qemu_mutex_lock_iothread() to bql_lock() | Stefan Hajnoczi |
| 2024-01-08 | Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging | Peter Maydell |
| 2024-01-06 | target/loongarch: move translate modules to tcg/ | Song Gao |
| 2024-01-06 | target/loongarch/meson: move gdbstub.c to loongarch.ss | Song Gao |
| 2024-01-05 | target/riscv: Fix mcycle/minstret increment behavior | Xu Lu |
