Age | Commit message (Expand) | Author |
2021-08-25 | target/arm: Implement MVE VPSEL | Peter Maydell |
2021-08-25 | target/arm: Implement MVE integer vector-vs-scalar comparisons | Peter Maydell |
2021-08-25 | target/arm: Implement MVE integer vector comparisons | Peter Maydell |
2021-08-25 | target/arm: Factor out gen_vpst() | Peter Maydell |
2021-08-25 | target/arm: Implement MVE incrementing/decrementing dup insns | Peter Maydell |
2021-08-25 | target/arm: Implement MVE VMULL (polynomial) | Peter Maydell |
2021-08-25 | target/arm: Fix VLDRB/H/W for predicated elements | Peter Maydell |
2021-08-25 | target/arm: Fix VPT advance when ECI is non-zero | Peter Maydell |
2021-08-25 | target/arm: Factor out mve_eci_mask() | Peter Maydell |
2021-08-25 | target/arm: Fix calculation of LTP mask when LR is 0 | Peter Maydell |
2021-08-25 | target/arm: Fix MVE 48-bit SQRSHRL for small right shifts | Peter Maydell |
2021-08-25 | target/arm: Fix 48-bit saturating shifts | Peter Maydell |
2021-08-25 | target/arm: Fix mask handling for MVE narrowing operations | Peter Maydell |
2021-08-25 | target/arm: Fix signed VADDV | Peter Maydell |
2021-08-25 | target/arm: Fix MVE VSLI by 0 and VSRI by <dt> | Peter Maydell |
2021-08-25 | target/arm: Print MVE VPR in CPU dumps | Peter Maydell |
2021-08-25 | target/arm: Note that we handle VMOVL as a special case of VSHLL | Peter Maydell |
2021-08-13 | target/i386: Fixed size of constant for Windows | Lara Lazier |
2021-07-30 | target/nios2: Mark raise_exception() as noreturn | Philippe Mathieu-Daudé |
2021-07-29 | Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ... | Peter Maydell |
2021-07-29 | target/i386: fix typo in ctl_has_irq | Paolo Bonzini |
2021-07-29 | target/i386: Added consistency checks for event injection | Lara Lazier |
2021-07-29 | i386: assert 'cs->kvm_state' is not null | Vitaly Kuznetsov |
2021-07-29 | target/ppc: Ease L=0 requirement on cmp/cmpi/cmpl/cmpli for ppc32 | Matheus Ferst |
2021-07-27 | target/arm: Add sve-default-vector-length cpu property | Richard Henderson |
2021-07-27 | target/arm: Export aarch64_sve_zcr_get_valid_len | Richard Henderson |
2021-07-27 | target/arm: Correctly bound length in sve_zcr_get_valid_len | Richard Henderson |
2021-07-27 | docs: Update path that mentions deprecated.rst | Mao Zhongyi |
2021-07-27 | target/arm: Report M-profile alignment faults correctly to the guest | Peter Maydell |
2021-07-27 | target/arm: Add missing 'return's after calling v7m_exception_taken() | Peter Maydell |
2021-07-27 | target/arm: Enforce that M-profile SP low 2 bits are always zero | Peter Maydell |
2021-07-26 | Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20210725' into staging | Peter Maydell |
2021-07-23 | i386: do not call cpudef-only models functions for max, host, base | Claudio Fontana |
2021-07-23 | target/i386: Added consistency checks for CR3 | Lara Lazier |
2021-07-22 | Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ... | Peter Maydell |
2021-07-22 | target/i386: Added consistency checks for EFER | Lara Lazier |
2021-07-22 | target/i386: Added consistency checks for CR4 | Lara Lazier |
2021-07-22 | target/i386: Added V_INTR_PRIO check to virtual interrupts | Lara Lazier |
2021-07-21 | target/hexagon: Drop include of qemu.h | Peter Maydell |
2021-07-21 | Hexagon (target/hexagon) remove put_user_*/get_user_* | Taylor Simpson |
2021-07-21 | accel/tcg: Remove TranslatorOps.breakpoint_check | Richard Henderson |
2021-07-21 | target/avr: Implement gdb_adjust_breakpoint | Richard Henderson |
2021-07-21 | target/i386: Implement debug_check_breakpoint | Richard Henderson |
2021-07-21 | target/arm: Implement debug_check_breakpoint | Richard Henderson |
2021-07-21 | target/alpha: Drop goto_tb path in gen_call_pal | Richard Henderson |
2021-07-21 | tcg: Rename helper_atomic_*_mmu and provide for user-only | Richard Henderson |
2021-07-18 | target/arm: Remove duplicate 'plus1' function from Neon and SVE decode | Peter Maydell |
2021-07-18 | target/arm: Fix offsets for TTBCR | Richard Henderson |
2021-07-15 | target/riscv: hardwire bits in hideleg and hedeleg | Jose Martins |
2021-07-15 | target/riscv: csr: Remove redundant check in fp csr read/write routines | Bin Meng |