slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2024-01-11	Merge tag 'pull-loongarch-20240111' of https://gitlab.com/gaosong/qemu into s...	Peter Maydell
2024-01-11	target/s390x: Fix LAE setting a wrong access register	Ilya Leoshkevich
2024-01-11	target/s390x/kvm/pv: Provide some more useful information if decryption fails	Thomas Huth
2024-01-11	hw/loongarch/virt: Set iocsr address space per-board rather than percpu	Bibo Mao
2024-01-11	target/loongarch: Add loongarch kvm into meson build	Tianrui Zhao
2024-01-11	target/loongarch: Implement set vcpu intr for kvm	Tianrui Zhao
2024-01-11	target/loongarch: Restrict TCG-specific code	Tianrui Zhao
2024-01-11	target/loongarch: Implement kvm_arch_handle_exit	Tianrui Zhao
2024-01-11	target/loongarch: Implement kvm_arch_init_vcpu	Tianrui Zhao
2024-01-11	target/loongarch: Implement kvm_arch_init function	Tianrui Zhao
2024-01-11	target/loongarch: Implement kvm get/set registers	Tianrui Zhao
2024-01-11	target/loongarch: Supplement vcpu env initial when vcpu reset	Tianrui Zhao
2024-01-11	target/loongarch: Define some kvm_arch interfaces	Tianrui Zhao
2024-01-11	Merge tag 'pull-target-arm-20240111' of https://git.linaro.org/people/pmaydel...	Peter Maydell
2024-01-10	target/riscv: Ensure mideleg is set correctly on reset	Alistair Francis
2024-01-10	target/riscv: Don't adjust vscause for exceptions	Alistair Francis
2024-01-10	target/riscv: Assert that the CSR numbers will be correct	Alistair Francis
2024-01-10	target/riscv: pmp: Ignore writes when RW=01 and MML=0	Ivan Klokov
2024-01-10	target/riscv/kvm: add RVV and Vector CSR regs	Daniel Henrique Barboza
2024-01-10	target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize()	Daniel Henrique Barboza
2024-01-10	target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1...	Yong-Xuan Wang
2024-01-10	target/riscv: add rva22s64 cpu	Daniel Henrique Barboza
2024-01-10	target/riscv: add RVA22S64 profile	Daniel Henrique Barboza
2024-01-10	target/riscv: add 'parent' in profile description	Daniel Henrique Barboza
2024-01-10	target/riscv: add satp_mode profile support	Daniel Henrique Barboza
2024-01-10	target/riscv/cpu.c: add riscv_cpu_is_32bit()	Daniel Henrique Barboza
2024-01-10	target/riscv/cpu.c: finalize satp_mode earlier	Daniel Henrique Barboza
2024-01-10	target/riscv: add priv ver restriction to profiles	Daniel Henrique Barboza
2024-01-10	target/riscv: implement svade	Daniel Henrique Barboza
2024-01-10	target/riscv: add 'rva22u64' CPU	Daniel Henrique Barboza
2024-01-10	riscv-qmp-cmds.c: add profile flags in cpu-model-expansion	Daniel Henrique Barboza
2024-01-10	target/riscv/tcg: validate profiles during finalize	Daniel Henrique Barboza
2024-01-10	target/riscv/tcg: honor user choice for G MISA bits	Daniel Henrique Barboza
2024-01-10	target/riscv/tcg: add hash table insert helpers	Daniel Henrique Barboza
2024-01-10	target/riscv/tcg: handle profile MISA bits	Daniel Henrique Barboza
2024-01-10	target/riscv/tcg: add riscv_cpu_write_misa_bit()	Daniel Henrique Barboza
2024-01-10	target/riscv/tcg: add MISA user options hash	Daniel Henrique Barboza
2024-01-10	target/riscv/tcg: add user flag for profile support	Daniel Henrique Barboza
2024-01-10	target/riscv/kvm: add 'rva22u64' flag as unavailable	Daniel Henrique Barboza
2024-01-10	target/riscv: add rva22u64 profile definition	Daniel Henrique Barboza
2024-01-10	riscv-qmp-cmds.c: expose named features in cpu_model_expansion	Daniel Henrique Barboza
2024-01-10	target/riscv/tcg: add 'zic64b' support	Daniel Henrique Barboza
2024-01-10	target/riscv: add zicbop extension flag	Daniel Henrique Barboza
2024-01-10	target/riscv: add rv64i CPU	Daniel Henrique Barboza
2024-01-10	target/riscv/tcg: update priv_ver on user_set extensions	Daniel Henrique Barboza
2024-01-10	target/riscv/tcg: do not use "!generic" CPU checks	Daniel Henrique Barboza
2024-01-10	target/riscv: create TYPE_RISCV_VENDOR_CPU	Daniel Henrique Barboza
2024-01-10	target/riscv: Add support for Zacas extension	Weiwei Li
2024-01-10	target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong()	Daniel Henrique Barboza
2024-01-10	target/riscv/kvm: add RISCV_CONFIG_REG()	Daniel Henrique Barboza