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2021-07-12Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' ↵Peter Maydell
into staging Add translator_use_goto_tb. Cleanups in prep of breakpoint fixes. Misc fixes. # gpg: Signature made Sat 10 Jul 2021 16:29:14 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210710: (41 commits) cpu: Add breakpoint tracepoints tcg: Remove TCG_TARGET_HAS_goto_ptr accel/tcg: Log tb->cflags with -d exec accel/tcg: Split out log_cpu_exec accel/tcg: Move tb_lookup to cpu-exec.c accel/tcg: Move helper_lookup_tb_ptr to cpu-exec.c target/i386: Use cpu_breakpoint_test in breakpoint_handler tcg: Fix prologue disassembly target/xtensa: Use translator_use_goto_tb target/tricore: Use tcg_gen_lookup_and_goto_ptr target/tricore: Use translator_use_goto_tb target/sparc: Use translator_use_goto_tb target/sh4: Use translator_use_goto_tb target/s390x: Remove use_exit_tb target/s390x: Use translator_use_goto_tb target/rx: Use translator_use_goto_tb target/riscv: Use translator_use_goto_tb target/ppc: Use translator_use_goto_tb target/openrisc: Use translator_use_goto_tb target/nios2: Use translator_use_goto_tb ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-07-11Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ↵Peter Maydell
staging * More SVM fixes (Lara) * Module annotation database (Gerd) * Memory leak fixes (myself) * Build fixes (myself) * --with-devices-* support (Alex) # gpg: Signature made Fri 09 Jul 2021 17:23:52 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini-gitlab/tags/for-upstream: (48 commits) meson: Use input/output for entitlements target configure: allow the selection of alternate config in the build configs: rename default-configs to configs and reorganise hw/arm: move CONFIG_V7M out of default-devices hw/arm: add dependency on OR_IRQ for XLNX_VERSAL meson: Introduce target-specific Kconfig meson: switch function tests from compilation to linking vl: fix leak of qdict_crumple return value target/i386: fix exceptions for MOV to DR target/i386: Added DR6 and DR7 consistency checks target/i386: Added MSRPM and IOPM size check monitor/tcg: move tcg hmp commands to accel/tcg, register them dynamically usb: build usb-host as module monitor/usb: register 'info usbhost' dynamically usb: drop usb_host_dev_is_scsi_storage hook monitor: allow register hmp commands accel: build tcg modular accel: add tcg module annotations accel: build qtest modular accel: add qtest module annotations ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-07-11Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier2/tags/trivial-branch-for-6.1-pull-request' into staging Trivial patches pull request 20210709 # gpg: Signature made Fri 09 Jul 2021 21:26:52 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-for-6.1-pull-request: util/guest-random: Fix size arg to tail memcpy migration: fix typo in mig_throttle_guest_down comment target/xtensa/xtensa-semi: Fix compilation problem on Haiku hw/virtio: Document *_should_notify() are called within rcu_read_lock() misc: Remove redundant new line in perror() virtiofsd: Add missing newline in error message misc: Fix "havn't" typo memory: Display MemoryRegion name in read/write ops trace events qemu-option: Drop dead assertion Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-07-11Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20210709' into staging target-arm queue: * New machine type: stm32vldiscovery * hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write * hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers * virt: Fix implementation of GPIO-based powerdown/shutdown mechanism * Correct the encoding of MDCCSR_EL0 and DBGDSCRint * hw/intc: Improve formatting of MEMTX_ERROR guest error message # gpg: Signature made Fri 09 Jul 2021 17:09:10 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210709: hw/intc: Improve formatting of MEMTX_ERROR guest error message target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint hw/arm/stellaris: Expand comment about handling of OLED chipselect hw/gpio/pl061: Document a shortcoming in our implementation hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset hw/arm/virt: Make PL061 GPIO lines pulled low, not high hw/gpio/pl061: Make pullup/pulldown of outputs configurable hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers hw/gpio/pl061: Document the interface of this device hw/gpio/pl061: Add tracepoints for register read and write hw/gpio/pl061: Clean up read/write offset handling logic hw/gpio/pl061: Convert DPRINTF to tracepoints hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write tests/boot-serial-test: Add STM32VLDISCOVERY board testcase docs/system: arm: Add stm32 boards description stm32vldiscovery: Add the STM32VLDISCOVERY Machine stm32f100: Add the stm32f100 SoC Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-07-09target/i386: Use cpu_breakpoint_test in breakpoint_handlerRichard Henderson
The loop is performing a simple boolean test for the existence of a BP_CPU breakpoint at EIP. Plus it gets the iteration wrong, if we happen to have a BP_GDB breakpoint at the same address. We have a function for this: cpu_breakpoint_test. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20210620062317.1399034-1-richard.henderson@linaro.org>
2021-07-09target/xtensa/xtensa-semi: Fix compilation problem on HaikuThomas Huth
The errno numbers are very large on Haiku, so the linking currently fails there with a "final link failed: memory exhausted" error message. We should not use the errno number as array indexes here, thus convert the code to a switch-case statement instead. A clever compiler should be able to optimize this code in a similar way anway. Reported-by: Richard Zak <richard.j.zak@gmail.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210706081822.1316551-1-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-07-09misc: Fix "havn't" typoPhilippe Mathieu-Daudé
Fix "havn't (make)" -> "haven't (made)" typo. Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210629051400.2573253-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-07-09target/xtensa: Use translator_use_goto_tbRichard Henderson
Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/tricore: Use tcg_gen_lookup_and_goto_ptrRichard Henderson
The non-single-step case of gen_goto_tb may use tcg_gen_lookup_and_goto_ptr to indirectly chain. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/tricore: Use translator_use_goto_tbRichard Henderson
Just use translator_use_goto_tb directly at the one call site, rather than maintaining a local wrapper. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/sparc: Use translator_use_goto_tbRichard Henderson
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/sh4: Use translator_use_goto_tbRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/s390x: Remove use_exit_tbRichard Henderson
We have not needed to end a TB for I/O since ba3e7926691 ("icount: clean up cpu_can_io at the entry to the block"). In use_goto_tb, the check for singlestep_enabled is in the generic translator_use_goto_tb. In s390x_tr_tb_stop, the check for singlestep_enabled is in the preceding do_debug test. Which leaves only FLAG_MASK_PER: fold that test alone into the two callers of use_exit tb. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/s390x: Use translator_use_goto_tbRichard Henderson
Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/rx: Use translator_use_goto_tbRichard Henderson
Just use translator_use_goto_tb directly at the one call site, rather than maintaining a local wrapper. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/riscv: Use translator_use_goto_tbRichard Henderson
Just use translator_use_goto_tb directly at the one call site, rather than maintaining a local wrapper. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/ppc: Use translator_use_goto_tbRichard Henderson
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/openrisc: Use translator_use_goto_tbRichard Henderson
Reorder the control statements to allow using the page boundary check from translator_use_goto_tb(). Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/nios2: Use translator_use_goto_tbRichard Henderson
Just use translator_use_goto_tb directly at the one call site, rather than maintaining a local wrapper. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/mips: Fix missing else in gen_goto_tbRichard Henderson
Do not emit dead code for the singlestep_enabled case, after having exited the TB with a debug exception. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/mips: Use translator_use_goto_tbRichard Henderson
Just use translator_use_goto_tb directly at the one call site, rather than maintaining a local wrapper. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/microblaze: Use translator_use_goto_tbRichard Henderson
Just use translator_use_goto_tb directly at the one call site, rather than maintaining a local wrapper. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/m68k: Use translator_use_goto_tbRichard Henderson
Just use translator_use_goto_tb directly at the one call site, rather than maintaining a local wrapper. Acked-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/i386: Use translator_use_goto_tbRichard Henderson
Just use translator_use_goto_tb directly at the one call site, rather than maintaining a local wrapper. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/hppa: Use translator_use_goto_tbRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/cris: Use translator_use_goto_tbRichard Henderson
The test for singlestepping is done in translator_use_goto_tb, so we may elide it from cris_tr_tb_stop. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/avr: Mark some helpers noreturnRichard Henderson
All of these helpers end with cpu_loop_exit. Reviewed-by: Michael Rolnik <mrolnik@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/avr: Use translator_use_goto_tbRichard Henderson
Single stepping is not the only reason not to use goto_tb. If goto_tb is disallowed, and single-stepping is not enabled, then use tcg_gen_lookup_and_goto_tb to indirectly chain. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/arm: Use translator_use_goto_tb for aarch32Richard Henderson
Just use translator_use_goto_tb directly at the one call site, rather than maintaining a local wrapper. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/arm: Use translator_use_goto_tb for aarch64Richard Henderson
We have not needed to end a TB for I/O since ba3e7926691 ("icount: clean up cpu_can_io at the entry to the block"), and gdbstub singlestep is handled by the generic function. Drop the unused 'n' argument to use_goto_tb. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/arm: Use DISAS_TOO_MANY for ISB and SBRichard Henderson
Using gen_goto_tb directly misses the single-step check. Let the branch or debug exception be emitted by arm_tr_tb_stop. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/alpha: Use translator_use_goto_tbRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/alpha: Remove in_superpageRichard Henderson
The number of links across (normal) pages using this is low, and it will shortly violate the contract for breakpoints. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/alpha: Remove use_exit_tbRichard Henderson
We have not needed to end a TB for I/O since ba3e7926691 ("icount: clean up cpu_can_io at the entry to the block"). We do not need to use exit_tb for singlestep, which only means generate one insn per TB. Which leaves only singlestep_enabled, which means raise a debug trap after every TB, which does not use exit_tb, which would leave the function mis-named. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09tcg: Avoid including 'trace-tcg.h' in target translate.cPhilippe Mathieu-Daudé
The root trace-events only declares a single TCG event: $ git grep -w tcg trace-events trace-events:115:# tcg/tcg-op.c trace-events:137:vcpu tcg guest_mem_before(TCGv vaddr, uint16_t info) "info=%d", "vaddr=0x%016"PRIx64" info=%d" and only a tcg/tcg-op.c uses it: $ git grep -l trace_guest_mem_before_tcg tcg/tcg-op.c therefore it is pointless to include "trace-tcg.h" in each target (because it is not used). Remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210629050935.2570721-1-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09meson: Introduce target-specific KconfigPhilippe Mathieu-Daudé
Add a target-specific Kconfig. We need the definitions in Kconfig so the minikconf tool can verify they exits. However CONFIG_FOO is only enabled for target foo via the meson.build rules. Two architecture have a particularity, ARM and MIPS. As their translators have been split you can potentially build a plain 32 bit build along with a 64-bit version including the 32-bit subset. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210131111316.232778-6-f4bug@amsat.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210707131744.26027-2-alex.bennee@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-07-09target/i386: fix exceptions for MOV to DRPaolo Bonzini
Use raise_exception_ra (without error code) when raising the illegal opcode operation; raise #GP when setting bits 63:32 of DR6 or DR7. Move helper_get_dr to sysemu/ since it is a privileged instruction that is not needed on user-mode emulators. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-07-09target/i386: Added DR6 and DR7 consistency checksLara Lazier
DR6[63:32] and DR7[63:32] are reserved and need to be zero. (AMD64 Architecture Programmer's Manual, V2, 15.5) Signed-off-by: Lara Lazier <laramglazier@gmail.com> Message-Id: <20210705081802.18960-3-laramglazier@gmail.com> [Ignore for 32-bit builds. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-07-09target/i386: Added MSRPM and IOPM size checkLara Lazier
The address of the last entry in the MSRPM and in the IOPM must be smaller than the largest physical address. (APM2 15.10-15.11) Signed-off-by: Lara Lazier <laramglazier@gmail.com> Message-Id: <20210705081802.18960-2-laramglazier@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-07-09target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRinthnick@vmware.com
Signed-off-by: Nick Hudson <hnick@vmware.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-07-09target/ppc: Support for H_RPT_INVALIDATE hcallBharata B Rao
If KVM_CAP_RPT_INVALIDATE KVM capability is enabled, then - indicate the availability of H_RPT_INVALIDATE hcall to the guest via ibm,hypertas-functions property. - Enable the hcall Both the above are done only if the new sPAPR machine capability cap-rpt-invalidate is set. Signed-off-by: Bharata B Rao <bharata@linux.ibm.com> Message-Id: <20210706112440.1449562-3-bharata@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-07-09target/ppc: Don't compile ppc_tlb_invalid_all without TCGLucas Mateus Castro (alqotel)
The function ppc_tlb_invalid_all is not compiled anymore in a TCG-less environment, and the call to that function has been disabled in this situation Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Message-Id: <20210708164957.28096-2-lucas.araujo@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-07-09target/ppc: Allow virtual hypervisor on CPU without HVBALATON Zoltan
Change the assert in ppc_store_sdr1() to allow vhyp to be set on CPUs without HV bit. This allows using the vhyp interface for firmware emulation on pegasos2. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <21c7745aabbb68fcc50bb2ffaf16b939ba21261c.1624811233.git.balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-07-09target/ppc: mtmsrd is an illegal instruction on BookENicholas Piggin
MSR is a 32-bit register in BookE and there is no mtmsrd instruction. Cc: Christian Zigotzky <chzigotzky@xenosoft.de> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20210706051321.609046-1-npiggin@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-07-09target/ppc: change ppc_hash32_xlate to use mmu_idxBruno Larsen (billionai)
Changed hash32 address translation to use the supplied mmu_idx, instead of using what was stored in the msr, for parity purposes (radix64 already uses that) and for conceptual correctness, all the relevant functions should always use the supplied mmu_idx, as there are no guarantees that the mmu_idx stored in the CPU variable will not desync. Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20210706150316.21005-3-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-07-09target/ppc: introduce mmu-books.hBruno Larsen (billionai)
Intrudoce a header common to all BookS MMUs, that can hold code that is common to hash32 and book3s-v3 MMUs. Suggested-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Message-Id: <20210706150316.21005-2-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-07-09target/ppc: changed ppc_hash64_xlate to use mmu_idxBruno Larsen (billionai)
Changed hash64 address translation to use the supplied mmu_idx instead of using the one stored in the msr, for parity purposes (other book3s MMUs already use it). Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210628133610.1143-4-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-07-09target/ppc: fix address translation bug for radix mmusBruno Larsen (billionai)
This commit attempts to fix a technical hiccup first mentioned by Richard Henderson in https://lists.nongnu.org/archive/html/qemu-devel/2021-05/msg06247.html To sumarize the hiccup here, when radix-style mmus are translating an address, they might need to call a second level of translation, with hypervisor privileges. However, the way it was being done up until this point meant that the second level translation had the same privileges as the first level. It could lead to a bug in address translation when running KVM inside a TCG guest, but this bug was never experienced by users, so this isn't as much a bug fix as it is a correctness cleanup. This patch attempts that cleanup by making radix64_*_xlate functions receive the mmu_idx, and passing one with the correct permission for the second level translation. The mmuidx macros added by this patch are only correct for non-bookE mmus, because BookE style set the IS and DS bits inverted and there might be other subtle differences. However, there doesn't seem to be BookE cpus that have radix-style mmus, so we left a comment there to document the issue, in case a machine does have that and was missed. As part of this cleanup, we now need to send the correct mmmu_idx when calling get_phys_page_debug, otherwise we might not be able to see the memory that the CPU could Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210628133610.1143-2-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-07-09target/ppc: Fix compilation with DEBUG_BATS debug optionFabiano Rosas
../target/ppc/mmu-hash32.c: In function 'ppc_hash32_bat_lookup': ../target/ppc/mmu-hash32.c:204:13: error: 'BATu' undeclared (first use in this function); 204 | BATu = &BATut[i]; | ^~~~ | BATut ../target/ppc/mmu-hash32.c:205:13: error: 'BATl' undeclared (first use in this function); 205 | BATl = &BATlt[i]; | ^~~~ | BATlt ../target/ppc/mmu-hash32.c:206:13: error: 'BEPIu' undeclared (first use in this function) 206 | BEPIu = *BATu & BATU32_BEPIU; | ^~~~~ ../target/ppc/mmu-hash32.c:206:29: error: 'BATU32_BEPIU' undeclared (first use in this function); 206 | BEPIu = *BATu & BATU32_BEPIU; | ^~~~~~~~~~~~ | BATU32_BEPI ../target/ppc/mmu-hash32.c:207:13: error: 'BEPIl' undeclared (first use in this function) 207 | BEPIl = *BATu & BATU32_BEPIL; | ^~~~~ ../target/ppc/mmu-hash32.c:207:29: error: 'BATU32_BEPIL' undeclared (first use in this function); 207 | BEPIl = *BATu & BATU32_BEPIL; | ^~~~~~~~~~~~ | BATU32_BEPI ../target/ppc/mmu-hash32.c:208:13: error: 'bl' undeclared (first use in this function) 208 | bl = (*BATu & 0x00001FFC) << 15; | ^~ Fixes: 9813279664 ("target-ppc: Disentangle BAT code for 32-bit hash MMUs") Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20210702215235.1941771-4-farosas@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-07-09target/ppc: Fix compilation with FLUSH_ALL_TLBS debug optionFabiano Rosas
../target/ppc/mmu_helper.c: In function 'helper_store_ibatu': ../target/ppc/mmu_helper.c:1802:17: error: unused variable 'cpu' [-Werror=unused-variable] 1802 | PowerPCCPU *cpu = env_archcpu(env); | ^~~ ../target/ppc/mmu_helper.c: In function 'helper_store_dbatu': ../target/ppc/mmu_helper.c:1838:17: error: unused variable 'cpu' [-Werror=unused-variable] 1838 | PowerPCCPU *cpu = env_archcpu(env); | ^~~ ../target/ppc/mmu_helper.c: In function 'helper_store_601_batu': ../target/ppc/mmu_helper.c:1874:17: error: unused variable 'cpu' [-Werror=unused-variable] 1874 | PowerPCCPU *cpu = env_archcpu(env); | ^~~ ../target/ppc/mmu_helper.c: In function 'helper_store_601_batl': ../target/ppc/mmu_helper.c:1919:17: error: unused variable 'cpu' [-Werror=unused-variable] 1919 | PowerPCCPU *cpu = env_archcpu(env); Fixes: db70b31144 ("target/ppc: Use env_cpu, env_archcpu") Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20210702215235.1941771-3-farosas@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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