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AgeCommit message (Expand)Author
2022-04-21Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into stagingRichard Henderson
2022-04-21compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau
2022-04-20Merge tag 'pull-ppc-20220420-2' of https://gitlab.com/danielhb/qemu into stagingRichard Henderson
2022-04-20Merge tag 'pull-tcg-20220420' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson
2022-04-20target/ppc: Add two missing register callbacks on POWER10Frederic Barrat
2022-04-20target/ppc: implement xscvqp[su]qzMatheus Ferst
2022-04-20target/ppc: implement xscv[su]qqpMatheus Ferst
2022-04-20target/ppc: Improve KVM hypercall traceFabiano Rosas
2022-04-20Merge tag 'pull-log-20220420' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson
2022-04-20Don't include sysemu/tcg.h if it is not necessaryThomas Huth
2022-04-20target/nios2: Remove log_cpu_state from resetRichard Henderson
2022-04-20exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson
2022-04-20*: Use fprintf between qemu_log_trylock/unlockRichard Henderson
2022-04-20util/log: Rename qemu_log_lock to qemu_log_trylockRichard Henderson
2022-04-20target/hexagon: Remove qemu_set_log in hexagon_translate_initRichard Henderson
2022-04-20target/i386: fix byte swap issue with XMM register accessAlex Bennée
2022-04-13target/i386: Remove unused XMMReg, YMMReg types and CPUState fieldsPeter Maydell
2022-04-13target/i386: do not access beyond the low 128 bits of SSE registersPaolo Bonzini
2022-04-06hw: hyperv: Initial commit for Synthetic Debugging deviceJon Doron
2022-04-06hyperv: Add support to process syndbg commandsJon Doron
2022-04-06hyperv: Add definitions for syndbgJon Doron
2022-04-06whpx: Added support for breakpoints and steppingIvan Shcherbakov
2022-04-06Remove qemu-common.h include from most unitsMarc-André Lureau
2022-04-06Move CPU softfloat unions to cpu-float.hMarc-André Lureau
2022-04-06include: move target page bits declaration to page-vary.hMarc-André Lureau
2022-04-06Replace qemu_real_host_page variables with inlined functionsMarc-André Lureau
2022-04-06Replace TARGET_WORDS_BIGENDIANMarc-André Lureau
2022-04-06Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau
2022-04-06Replace qemu_gettimeofday() with g_get_real_time()Marc-André Lureau
2022-04-06qapi, target/i386/sev: Add cpu0-id to query-sev-capabilitiesDov Murik
2022-04-02Merge tag 'pull-request-2022-04-01' of https://gitlab.com/thuth/qemu into sta...Peter Maydell
2022-04-01Merge tag 'pull-target-arm-20220401' of https://git.linaro.org/people/pmaydel...Peter Maydell
2022-04-01Merge tag 'pull-riscv-to-apply-20220401' of github.com:alistair23/qemu into s...Peter Maydell
2022-04-01target/arm: Don't use DISAS_NORETURN in STXP !HAVE_CMPXCHG128 codegenPeter Maydell
2022-04-01target/arm: Determine final stage 2 output PA space based on original IPAIdan Horowitz
2022-04-01target/arm: Take VSTCR.SW, VTCR.NSW into account in final stage 2 walkIdan Horowitz
2022-04-01target/arm: Check VSTCR.SW when assigning the stage 2 output PA spaceIdan Horowitz
2022-04-01target/arm: Fix MTE access checks for disabled SEL2Idan Horowitz
2022-04-01target/s390x: Fix determination of overflow condition code after subtractionBruno Haible
2022-04-01target/s390x: Fix determination of overflow condition code after additionBruno Haible
2022-04-01target/riscv: rvv: Add missing early exit condition for whole register load/s...Yueh-Ting (eop) Chen
2022-04-01target/riscv: Avoid leaking "no translation" TLB entriesPalmer Dabbelt
2022-03-31target/sh4: Remove old README.sh4 fileThomas Huth
2022-03-29target/mips: Fix address space range declaration on n32WANG Xuerui
2022-03-26target/ppc: fix helper_xvmadd* argument orderMatheus Ferst
2022-03-25target/arm: Fix sve_ld1_z and sve_st1_z vs MMIORichard Henderson
2022-03-25Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell
2022-03-24target/i386: properly reset TSC on resetPaolo Bonzini
2022-03-24target/i386: tcg: high bits SSE cmp operation must be ignoredPaolo Bonzini
2022-03-23KVM: x86: workaround invalid CPUID[0xD,9] info on some AMD processorsPaolo Bonzini
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