aboutsummaryrefslogtreecommitdiff
path: root/target
AgeCommit message (Collapse)Author
2023-11-07target/mips: Fix MSA BZ/BNZ opcodes displacementPhilippe Mathieu-Daudé
The PC offset is *signed*. Cc: qemu-stable@nongnu.org Reported-by: Sergey Evlashev <vectorchiefrocks@gmail.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1624 Fixes: c7a9ef7517 ("target/mips: Introduce decode tree bindings for MSA ASE") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914085807.12241-1-philmd@linaro.org>
2023-11-07target/i386/monitor: synchronize cpu state for lapic infoDongli Zhang
While the default "info lapic" always synchronizes cpu state ... mon_get_cpu() -> mon_get_cpu_sync(mon, true) -> cpu_synchronize_state(cpu) -> ioctl KVM_GET_LAPIC (taking KVM as example) ... the cpu state is not synchronized when the apic-id is available as argument. The cpu state should be synchronized when apic-id is available. Otherwise the "info lapic <apic-id>" always returns stale data. Reference: https://lore.kernel.org/all/20211028155457.967291-19-berrange@redhat.com/ Cc: Joe Jin <joe.jin@oracle.com> Signed-off-by: Dongli Zhang <dongli.zhang@oracle.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: David Woodhouse <dwmw@amazon.co.uk> Message-ID: <20231030085336.2681386-1-armbru@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231026211938.162815-1-dongli.zhang@oracle.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-11-07target/i386/kvm: Correct comment in kvm_cpu_realize()Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230918160257.30127-4-philmd@linaro.org>
2023-11-07target/i386/hvf: Rename 'X86CPU *x86_cpu' variable as 'cpu'Philippe Mathieu-Daudé
Follow the naming used by other files in target/i386/. No functional changes. Suggested-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20231020111136.44401-4-philmd@linaro.org>
2023-11-07target/i386/hvf: Rename 'CPUState *cpu' variable as 'cs'Philippe Mathieu-Daudé
Follow the naming used by other files in target/i386/. No functional changes. Suggested-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20231020111136.44401-3-philmd@linaro.org>
2023-11-07target/i386/hvf: Use CPUState typedefPhilippe Mathieu-Daudé
Follow C style guidelines and use CPUState forward declaration from "qemu/typedefs.h". No functional changes. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20231020111136.44401-2-philmd@linaro.org>
2023-11-07target/i386/hvf: Use env_archcpu() in simulate_[rdmsr/wrmsr]()Philippe Mathieu-Daudé
When CPUArchState* is available (here CPUX86State*), we can use the fast env_archcpu() macro to get ArchCPU* (here X86CPU*). The QOM cast X86_CPU() macro will be slower when building with --enable-qom-cast-debug. Pass CPUX86State* as argument to simulate_rdmsr / simulate_wrmsr instead of a CPUState* to avoid an extra cast. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Roman Bolshakov <roman@roolebo.dev> Tested-by: Roman Bolshakov <roman@roolebo.dev> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20231009110239.66778-7-philmd@linaro.org>
2023-11-07target/i386/hvf: Use x86_cpu in simulate_[rdmsr|wrmsr]()Philippe Mathieu-Daudé
We already have 'x86_cpu = X86_CPU(cpu)'. Use the variable instead of doing another QOM cast with X86_CPU(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Roman Bolshakov <roman@roolebo.dev> Tested-by: Roman Bolshakov <roman@roolebo.dev> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20231009110239.66778-6-philmd@linaro.org>
2023-11-07target/xtensa: Use env_archcpu() in update_c[compare|count]()Philippe Mathieu-Daudé
When CPUArchState* is available (here CPUXtensaState*), we can use the fast env_archcpu() macro to get ArchCPU* (here XtensaCPU*). The QOM cast XTENSA_CPU() macro will be slower when building with --enable-qom-cast-debug. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20231009110239.66778-5-philmd@linaro.org>
2023-11-07target/s390x: Use env_archcpu() in handle_diag_308()Philippe Mathieu-Daudé
When CPUArchState* is available (here CPUS390XState*), we can use the fast env_archcpu() macro to get ArchCPU* (here S390CPU*). The QOM cast S390_CPU() macro will be slower when building with --enable-qom-cast-debug. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20231009110239.66778-4-philmd@linaro.org>
2023-11-07target/riscv: Use env_archcpu() in [check_]nanbox()Philippe Mathieu-Daudé
When CPUArchState* is available (here CPURISCVState*), we can use the fast env_archcpu() macro to get ArchCPU* (here RISCVCPU*). The QOM cast RISCV_CPU() macro will be slower when building with --enable-qom-cast-debug. Inspired-by: Richard W.M. Jones <rjones@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Richard W.M. Jones <rjones@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20231009110239.66778-3-philmd@linaro.org>
2023-11-07target/ppc: Use env_archcpu() in helper_book3s_msgsndp()Philippe Mathieu-Daudé
When CPUArchState* is available (here CPUPPCState*), we can use the fast env_archcpu() macro to get ArchCPU* (here PowerPCCPU*). The QOM cast POWERPC_CPU() macro will be slower when building with --enable-qom-cast-debug. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20231009110239.66778-2-philmd@linaro.org>
2023-11-07target/riscv: Move TYPE_RISCV_CPU_BASE definition to 'cpu.h'Philippe Mathieu-Daudé
TYPE_RISCV_CPU_BASE depends on the TARGET_RISCV32/TARGET_RISCV64 definitions which are target specific. Such target specific definition taints "cpu-qom.h". Since "cpu-qom.h" must be target agnostic, remove its target specific definition uses by moving TYPE_RISCV_CPU_BASE to "target/riscv/cpu.h". "target/riscv/cpu-qom.h" is now fully target agnostic. Add a comment clarifying that in the header. Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013140116.255-12-philmd@linaro.org>
2023-11-07target/openrisc: Declare QOM definitions in 'cpu-qom.h'Philippe Mathieu-Daudé
"target/foo/cpu.h" contains the target specific declarations. A heterogeneous setup need to access target agnostic declarations (at least the QOM ones, to instantiate the objects). Our convention is to add such target agnostic QOM declarations in the "target/foo/cpu-qom.h" header. Add a comment clarifying that in the header. Extract QOM definitions from "cpu.h" to "cpu-qom.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013140116.255-11-philmd@linaro.org>
2023-11-07target/nios2: Declare QOM definitions in 'cpu-qom.h'Philippe Mathieu-Daudé
"target/foo/cpu.h" contains the target specific declarations. A heterogeneous setup need to access target agnostic declarations (at least the QOM ones, to instantiate the objects). Our convention is to add such target agnostic QOM declarations in the "target/foo/cpu-qom.h" header. Add a comment clarifying that in the header. Extract QOM definitions from "cpu.h" to "cpu-qom.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013140116.255-10-philmd@linaro.org>
2023-11-07target/loongarch: Declare QOM definitions in 'cpu-qom.h'Philippe Mathieu-Daudé
"target/foo/cpu.h" contains the target specific declarations. A heterogeneous setup need to access target agnostic declarations (at least the QOM ones, to instantiate the objects). Our convention is to add such target agnostic QOM declarations in the "target/foo/cpu-qom.h" header. Add a comment clarifying that in the header. Extract QOM definitions from "cpu.h" to "cpu-qom.h". Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013140116.255-9-philmd@linaro.org>
2023-11-07target/hexagon: Declare QOM definitions in 'cpu-qom.h'Philippe Mathieu-Daudé
"target/foo/cpu.h" contains the target specific declarations. A heterogeneous setup need to access target agnostic declarations (at least the QOM ones, to instantiate the objects). Our convention is to add such target agnostic QOM declarations in the "target/foo/cpu-qom.h" header. Add a comment clarifying that in the header. Extract QOM definitions from "cpu.h" to "cpu-qom.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20231013140116.255-8-philmd@linaro.org>
2023-11-07target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'Philippe Mathieu-Daudé
Hegerogeneous code needs access to the FOO_CPU_TYPE_NAME() macro to resolve target CPU types. Move the declaration (along with the required FOO_CPU_TYPE_SUFFIX) to "cpu-qom.h". "target/foo/cpu-qom.h" is supposed to be target agnostic (include-able by any target). Add such mention in the header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013140116.255-7-philmd@linaro.org>
2023-11-07target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'Philippe Mathieu-Daudé
CPU_RESOLVING_TYPE is a per-target definition, and is irrelevant for other targets. Move it to "cpu.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013140116.255-6-philmd@linaro.org>
2023-11-07target/ppc: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'Philippe Mathieu-Daudé
CPU_RESOLVING_TYPE is a per-target definition, and is irrelevant for other targets. Move it to "cpu.h". "target/ppc/cpu-qom.h" is supposed to be target agnostic (include-able by any target). Add such mention in the header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013140116.255-5-philmd@linaro.org>
2023-11-07target/arm: Move internal declarations from 'cpu-qom.h' to 'cpu.h'Philippe Mathieu-Daudé
These definitions and declarations are only used by target/arm/, no need to expose them to generic hw/. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013140116.255-4-philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <c48c9829-3dfa-79cf-3042-454fda0d00dc@linaro.org>
2023-11-07target: Mention 'cpu-qom.h' is target agnosticPhilippe Mathieu-Daudé
"target/foo/cpu-qom.h" is supposed to be target agnostic (include-able by any target). Add such mention in the header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013140116.255-3-philmd@linaro.org>
2023-11-07target: Unify QOM stylePhilippe Mathieu-Daudé
Enforce the style described by commit 067109a11c ("docs/devel: mention the spacing requirement for QOM"): The first declaration of a storage or class structure should always be the parent and leave a visual space between that declaration and the new code. It is also useful to separate backing for properties (options driven by the user) and internal state to make navigation easier. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20231013140116.255-2-philmd@linaro.org>
2023-11-07Merge tag 'pull-xenfv.for-upstream-20231107' of ↵Stefan Hajnoczi
git://git.infradead.org/users/dwmw2/qemu into staging Xen PV guest support for 8.2 Add Xen PV console and network support, the former of which enables the Xen "PV shim" to be used to support PV guests. Also clean up the block support and make it work when the user passes just 'drive file=IMAGE,if=xen' on the command line. Update the documentation to reflect all of these, taking the opportunity to simplify what it says about q35 by making unplug work for AHCI. Ignore the VCPU_SSHOTTMR_future timer flag, and advertise the 'fixed' per-vCPU upcall vector support, as newer upstream Xen do. # -----BEGIN PGP SIGNATURE----- # # iQJIBAABCAAyFiEEvgfZ/VSAmrLEsP9fY3Ys2mfi81kFAmVJ/7EUHGR3bXcyQGlu # ZnJhZGVhZC5vcmcACgkQY3Ys2mfi81k+/xAAswivVR4+nwz3wTSN7EboGogS3hy+ # ZsTpvbJnfprGQJAK8vv8OP4eunaCJkO/dy3M/33Dh270msmV6I/1ki0E1RIPG45D # n5wKM1Zxk0ABvjIgdp3xiLwITTdruJ+k9aqV8U9quhjgNFdOa7yjBOG8MD32GEPZ # KHbavJ++huOu7+DZHJRNRq4gI/fREIULoPGHVg7WuEiRDYokOOmMROXqmTHTaUkV # yFhkofzWxlpYhh7qRQx6/A80CSf7xwCof8krjdMCOYj3XGzYVZND0z5ZfHQYEwqt # fowhargA8gH4V3d21S/MWCaZ+QrswFXZhcnl5wuGgWakV4ChvFETKs+fz2mODWUx # 2T13trqeFJ5ElTrSpH1iWCoSEy6KCeLecvx7c/6HPSkDYQ3w5q8dXPpqgEtXY24S # Wcmw4PkQ+HrLX7wbSU7QLyTZjvCQLFZ3Sb0uTf2zwsJZyeCCiT2lqAaogoMm6Kg0 # m/jG1JzE+9AC3j0Upp1lS3EK1qdxIuLdBuIcaEBEjy7Am+Y14PlZYoU2c751KbRF # kqnIOYMoijX0PJDomPqCQtYNE0mrtogo0AbcFFIu+4k25vGbkl7xS5p2du9qw2Rd # ++IdqQYzdzrUcIwmxocFQqFBJQ2dcbOGB1d7+VJ+A1Uj3yY2/DnFG5WqSaqS0KJi # ZhBdFs3OTlPnRoM= # =Dg79 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Nov 2023 17:13:21 HKT # gpg: using RSA key BE07D9FD54809AB2C4B0FF5F63762CDA67E2F359 # gpg: issuer "dwmw2@infradead.org" # gpg: Good signature from "David Woodhouse <dwmw2@infradead.org>" [unknown] # gpg: aka "David Woodhouse <dwmw2@exim.org>" [unknown] # gpg: aka "David Woodhouse <david@woodhou.se>" [unknown] # gpg: aka "David Woodhouse <dwmw2@kernel.org>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: BE07 D9FD 5480 9AB2 C4B0 FF5F 6376 2CDA 67E2 F359 * tag 'pull-xenfv.for-upstream-20231107' of git://git.infradead.org/users/dwmw2/qemu: docs: update Xen-on-KVM documentation xen-platform: unplug AHCI disks hw/i386/pc: support '-nic' for xen-net-device hw/xen: update Xen PV NIC to XenDevice model hw/xen: only remove peers of PCI NICs on unplug hw/xen: add support for Xen primary console in emulated mode hw/xen: update Xen console to XenDevice model hw/xen: do not repeatedly try to create a failing backend device hw/xen: add get_frontend_path() method to XenDeviceClass hw/xen: automatically assign device index to block devices hw/xen: populate store frontend nodes with XenStore PFN/port i386/xen: advertise XEN_HVM_CPUID_UPCALL_VECTOR in CPUID include: update Xen public headers to Xen 4.17.2 release hw/xen: Clean up event channel 'type_val' handling to use union i386/xen: Ignore VCPU_SSHOTTMR_future flag in set_singleshot_timer() Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-07hw/xen: add support for Xen primary console in emulated modeDavid Woodhouse
The primary console is special because the toolstack maps a page into the guest for its ring, and also allocates the guest-side event channel. The guest's grant table is even primed to export that page using a known grant ref#. Add support for all that in emulated mode, so that we can have a primary console. For reasons unclear, the backends running under real Xen don't just use a mapping of the well-known GNTTAB_RESERVED_CONSOLE grant ref (which would also be in the ring-ref node in XenStore). Instead, the toolstack sets the ring-ref node of the primary console to the GFN of the guest page. The backend is expected to handle that special case and map it with foreignmem operations instead. We don't have an implementation of foreignmem ops for emulated Xen mode, so just make it map GNTTAB_RESERVED_CONSOLE instead. This would probably work for real Xen too, but we can't work out how to make real Xen create a primary console of type "ioemu" to make QEMU drive it, so we can't test that; might as well leave it as it is for now under Xen. Now at last we can boot the Xen PV shim and run PV kernels in QEMU. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org>
2023-11-07i386/xen: advertise XEN_HVM_CPUID_UPCALL_VECTOR in CPUIDDavid Woodhouse
This will allow Linux guests (since v6.0) to use the per-vCPU upcall vector delivered as MSI through the local APIC. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org>
2023-11-07i386/xen: Ignore VCPU_SSHOTTMR_future flag in set_singleshot_timer()David Woodhouse
Upstream Xen now ignores this flag¹, since the only guest kernel ever to use it was buggy. ¹ https://xenbits.xen.org/gitweb/?p=xen.git;a=commitdiff;h=19c6cbd909 Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org>
2023-11-07Merge tag 'pull-pa-20231106' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi
target/hppa: Implement PA2.0 instructions hw/hppa: Map astro chip 64-bit I/O mem hw/hppa: Turn on 64-bit cpu for C3700 # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmVJqDEdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8n5Qf/R15CvXGMgjDJjoV2 # ILMFM+Rpg17SR2yu060sEZ01R3iHdobeCcDB184K0RI9JLrpcBFar+PeF023o9fn # O9MnfIyL6/ggzaeIpQ9AD2uT0HJMU9hLFoyQqQvnhDHHcT34raL2+Zkrkb2vvauH # XET7awXN9xYCnY4ALrfcapzlrHqI77ahz0vReUWPxk7eGY2ez8dEOiFW2WLBmuMx # mAFAMrFQhq66GjoMDl8JiGHD/KBJQ9X4eUAEotS27lTCOYU0ryA6dWBGqBSTWCUa # smpxkeGQKOew+717HV1H4FdCRYG1Rgm7yFN423JULeew+T7DHvfe0K55vMIulx5I # g3oVZA== # =dxC7 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Nov 2023 11:00:01 HKT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-pa-20231106' of https://gitlab.com/rth7680/qemu: (85 commits) hw/hppa: Allow C3700 with 64-bit and B160L with 32-bit CPU only hw/hppa: Turn on 64-bit CPU for C3700 machine hw/pci-host/astro: Trigger CPU irq on CPU HPA in high memory hw/pci-host/astro: Map Astro chip into 64-bit I/O memory region target/hppa: Improve interrupt logging target/hppa: Update IIAOQ, IIASQ for pa2.0 target/hppa: Create raise_exception_with_ior target/hppa: Add unwind_breg to CPUHPPAState target/hppa: Clear upper bits in mtctl for pa1.x target/hppa: Avoid async_safe_run_on_cpu on uniprocessor system target/hppa: Add pa2.0 cpu local tlb flushes target/hppa: Implement pa2.0 data prefetch instructions linux-user/hppa: Drop EXCP_DUMP from handled exceptions hw/hppa: Translate phys addresses for the cpu include/hw/elf: Remove truncating signed casts target/hppa: Return zero for r0 from load_gpr target/hppa: Precompute zero into DisasContext target/hppa: Fix interruption based on default PSW target/hppa: Implement PERMH target/hppa: Implement MIXH, MIXW ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-07Merge tag 'pull-riscv-to-apply-20231107' of ↵Stefan Hajnoczi
https://github.com/alistair23/qemu into staging Third RISC-V PR for 8.2 * Rename ext_icboz to ext_zicboz * Rename ext_icbom to ext_zicbom * Rename ext_icsr to ext_zicsr * Rename ext_ifencei to ext_zifencei * Add RISC-V Virtual IRQs and IRQ filtering support * Change default linux-user cpu to 'max' * Update 'virt' machine core limit * Add query-cpu-model-expansion API * Rename epmp to smepmp and expose the extension * Clear pmp/smepmp bits on reset * Ignore pmp writes when RW=01 * Support zicntr/zihpm flags and disable support * Correct CSR_MSECCFG operations * Update mail address for Weiwei Li * Update RISC-V vector crypto to ratified v1.0.0 * Clear the Ibex/OpenTitan SPI interrupts even if disabled * Set the OpenTitan priv to 1.12.0 * Support discontinuous PMU counters # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmVJoOEACgkQr3yVEwxT # gBPwcw/5AXgSVu521IHpobofq4Skc2rpO9P0Hep3IniBuS+5+h2XM3fwWNBaeeGj # LZgdXDrCfcCnPuFh2I5j1D885xJDncDF4LET9EFtxK+BTT8eC5JpaCnORdV3Zd2T # C7qdq1r4J/wKBel3cAz1jlLXc2Pssle4NFaMZGmOGlNX/mLJUYkI6BwKG9wNiCI+ # cCRQW5bEv9g8XzPYPsIKhX9aTegDKdV5x4Xj3YyVs8qkZTVM7Ona8GTpy6eShNfL # h/RW+yvSxLwfKC9YJHesjI1oqhLsAuA7hFu5AVHiedFNAD5FevMZsZwrqjrmeBOG # 5awBw9XgfXFFl7jQ0VQVRknt/PFANzTmGGbjLUkaXgJ6iTmH7oIMzwbkx2pM/0Qd # HV2EboUPe5rJl0SNhcDMCJkYJYpt4z6TVXFpN5p10WU4K1AJXZf9P3YkChcxWiSK # B4DlY4ax3W77voySwbKCvJRIRWCFQZmtl7doFY5dEQz2ERcNfI7VIB1GKIj7BlGm # AVTCc5G9KghsaB8q0BzYbDplzCggdaaUBRgpIgLS/n22GKJlOisFwMCawWquPkEw # i0t3ftt+Ket4Qnnq+dO4W3ehR4qW1/XatCWgQ3NCSgUeS4/9VK3h/nz5t+L7iKwp # mjp86gNN11wcJRsBIIV7nOAmSAs9ybCm2F4J6YAyh3n1IlRVN0Q= # =2A+W # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Nov 2023 10:28:49 HKT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20231107' of https://github.com/alistair23/qemu: (49 commits) docs/about/deprecated: Document RISC-V "pmu-num" deprecation target/riscv: Add "pmu-mask" property to replace "pmu-num" target/riscv: Use existing PMU counter mask in FDT generation target/riscv: Don't assume PMU counters are continuous target/riscv: Propagate error from PMU setup target/riscv: cpu: Set the OpenTitan priv to 1.12.0 hw/ssi: ibex_spi_host: Clear the interrupt even if disabled disas/riscv: Replace TABs with space disas/riscv: Add support for vector crypto extensions disas/riscv: Add rv_codec_vror_vi for vror.vi disas/riscv: Add rv_fmt_vd_vs2_uimm format target/riscv: Move vector crypto extensions to riscv_cpu_extensions target/riscv: Expose Zvks[c|g] extnesion properties target/riscv: Add cfg properties for Zvks[c|g] extensions target/riscv: Expose Zvkn[c|g] extnesion properties target/riscv: Add cfg properties for Zvkn[c|g] extensions target/riscv: Expose Zvkb extension property target/riscv: Replace Zvbb checking by Zvkb target/riscv: Add cfg property for Zvkb extension target/riscv: Expose Zvkt extension property ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-06target/hppa: Improve interrupt loggingRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Update IIAOQ, IIASQ for pa2.0Richard Henderson
These registers have a different format for pa2.0. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Create raise_exception_with_iorRichard Henderson
Handle pa2.0 logic for filling in ISR+IOR. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Add unwind_breg to CPUHPPAStateRichard Henderson
Fill in the insn_start value during form_gva, and copy it out to the env field in hppa_restore_state_to_opc. The value is not yet consumed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Clear upper bits in mtctl for pa1.xHelge Deller
Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Avoid async_safe_run_on_cpu on uniprocessor systemRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Add pa2.0 cpu local tlb flushesHelge Deller
The previous decoding misnamed the bit it called "local". Other than the name, the implementation was correct for pa1.x. Rename this field to "tlbe". PA2.0 adds (a real) local bit to PxTLB, and also adds a range of pages to flush in GR[b]. Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement pa2.0 data prefetch instructionsRichard Henderson
These are aliased onto the normal integer loads to %g0. Since we don't emulate caches, prefetch is a nop. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Return zero for r0 from load_gprRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Precompute zero into DisasContextRichard Henderson
Reduce the number of times we look for the constant 0. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Fix interruption based on default PSWHelge Deller
The default PSW is set by the operating system with the PDC_PSW firmware call. Use that setting to decide if wide mode is to be enabled for interruptions and EIRR usage. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement PERMHRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement MIXH, MIXWRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HSHLADD, HSHRADDRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HSHL, HSHRRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HAVGRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HSUBRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HADDRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64Richard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Use tcg_temp_new_i64 not tcg_temp_newRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Adjust vmstate_env for pa2.0 tlbRichard Henderson
Split out the tlb to a subsection so that it can be separately versioned -- the format is only partially following the architecture and is partially guided by the qemu implementation. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-15 06:41:02 +0000