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2023-09-01target/i386: Add support for AMX-COMPLEX in CPUID enumerationTao Su
Latest Intel platform GraniteRapids-D introduces AMX-COMPLEX, which adds two instructions to perform matrix multiplication of two tiles containing complex elements and accumulate the results into a packed single precision tile. AMX-COMPLEX is enumerated via CPUID.(EAX=7,ECX=1):EDX[bit 8]. Add the CPUID definition for AMX-COMPLEX, AMX-COMPLEX will be enabled automatically when using '-cpu host' and KVM advertises AMX-COMPLEX to userspace. Signed-off-by: Tao Su <tao1.su@linux.intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-ID: <20230830074324.84059-1-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-01target/i386: fix memory operand size for CVTPS2PDPaolo Bonzini
CVTPS2PD only loads a half-register for memory, unlike the other operations under 0x0F 0x5A. "Unpack" the group into separate emission functions instead of using gen_unary_fp_sse. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-01target/i386: generalize operand size "ph" for use in CVTPS2PDPaolo Bonzini
CVTPS2PD only loads a half-register for memory, like CVTPH2PS. It can reuse the "ph" packed half-precision size to load a half-register, but rename it to "xh" because it is now a variation of "x" (it is not used only for half-precision values). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-01target/i386: raise FERR interrupt with iothread lockedPaolo Bonzini
Otherwise tcg_handle_interrupt() triggers an assertion failure: #5 0x0000555555c97369 in tcg_handle_interrupt (cpu=0x555557434cb0, mask=2) at ../accel/tcg/tcg-accel-ops.c:83 #6 tcg_handle_interrupt (cpu=0x555557434cb0, mask=2) at ../accel/tcg/tcg-accel-ops.c:81 #7 0x0000555555b4d58b in pic_irq_request (opaque=<optimized out>, irq=<optimized out>, level=1) at ../hw/i386/x86.c:555 #8 0x0000555555b4f218 in gsi_handler (opaque=0x5555579423d0, n=13, level=1) at ../hw/i386/x86.c:611 #9 0x00007fffa42bde14 in code_gen_buffer () #10 0x0000555555c724bb in cpu_tb_exec (cpu=cpu@entry=0x555557434cb0, itb=<optimized out>, tb_exit=tb_exit@entry=0x7fffe9bfd658) at ../accel/tcg/cpu-exec.c:457 Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1808 Reported-by: NyanCatTW1 <https://gitlab.com/a0939712328> Co-developed-by: Richard Henderson <richard.henderson@linaro.org>' Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-08-31hw/mips: spelling fixesMichael Tokarev
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230823065335.1919380-7-mjt@tls.msk.ru> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-08-31target/xtensa: Include missing 'qemu/atomic.h' headerPhilippe Mathieu-Daudé
Since commit fa92bd4af7 ("target/xtensa: fix access to the INTERRUPT SR") these files use QEMU atomic API. Explicit the header inclusion instead of relying on implicit and indirect inclusion. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230828221314.18435-10-philmd@linaro.org>
2023-08-31target/mips: Remove unused headers in lcsr_helper.cPhilippe Mathieu-Daudé
This files only access the address_space_ld/st API, declared in "exec/cpu-all.h", already included by "cpu.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230828221314.18435-9-philmd@linaro.org>
2023-08-31target/helpers: Remove unnecessary 'qemu/main-loop.h' headerPhilippe Mathieu-Daudé
"qemu/main-loop.h" declares functions related to QEMU's main loop mutex, which these files don't access. Remove the unused "qemu/main-loop.h" header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230828221314.18435-8-philmd@linaro.org>
2023-08-31target/helpers: Remove unnecessary 'exec/cpu_ldst.h' headerPhilippe Mathieu-Daudé
These files don't use the CPU ld/st API, remove the unnecessary "exec/cpu_ldst.h" header. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230828221314.18435-7-philmd@linaro.org>
2023-08-31target/translate: Remove unnecessary 'exec/cpu_ldst.h' headerPhilippe Mathieu-Daudé
All these files only access the translator_ld/st API declared in "exec/translator.h". The CPU ld/st API from declared in "exec/cpu_ldst.h" is not used, remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230828221314.18435-5-philmd@linaro.org>
2023-08-31target/translate: Include missing 'exec/cpu_ldst.h' headerPhilippe Mathieu-Daudé
All these files access the CPU LD/ST API declared in "exec/cpu_ldst.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230828221314.18435-4-philmd@linaro.org>
2023-08-31target/riscv/pmu: Restrict 'qemu/log.h' include to sourcePhilippe Mathieu-Daudé
Declarations from "riscv/pmu.h" don't need anything from "qemu/log.h", reduce it's inclusion to the source. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230828221314.18435-3-philmd@linaro.org>
2023-08-31target/ppc/pmu: Include missing 'qemu/timer.h' headerPhilippe Mathieu-Daudé
Since commit c2eff582a3 ("target/ppc: PMU basic cycle count for pseries TCG") pmu_update_cycles() uses QEMU_CLOCK_VIRTUAL and calls qemu_clock_get_ns(), both defined in "qemu/timer.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230828221314.18435-2-philmd@linaro.org>
2023-08-31bulk: Do not declare function prototypes using 'extern' keywordPhilippe Mathieu-Daudé
By default, C function prototypes declared in headers are visible, so there is no need to declare them as 'extern' functions. Remove this redundancy in a single bulk commit; do not modify: - meson.build (used to check function availability at runtime) - pc-bios/ - libdecnumber/ - tests/ - *.c Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20230605175647.88395-5-philmd@linaro.org>
2023-08-31accel: Remove HAX acceleratorPhilippe Mathieu-Daudé
HAX is deprecated since commits 73741fda6c ("MAINTAINERS: Abort HAXM maintenance") and 90c167a1da ("docs/about/deprecated: Mark HAXM in QEMU as deprecated"), released in v8.0.0. Per the latest HAXM release (v7.8 [*]), the latest QEMU supported is v7.2: Note: Up to this release, HAXM supports QEMU from 2.9.0 to 7.2.0. The next commit (https://github.com/intel/haxm/commit/da1b8ec072) added: HAXM v7.8.0 is our last release and we will not accept pull requests or respond to issues after this. It became very hard to build and test HAXM. Its previous maintainers made it clear they won't help. It doesn't seem to be a very good use of QEMU maintainers to spend their time in a dead project. Save our time by removing this orphan zombie code. [*] https://github.com/intel/haxm/releases/tag/v7.8.0 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230831082016.60885-1-philmd@linaro.org>
2023-08-31target/s390x: Define TARGET_HAS_PRECISE_SMCIlya Leoshkevich
PoP (Sequence of Storage References -> Instruction Fetching) says: ... if a store that is conceptually earlier is made by the same CPU using the same effective address as that by which the instruction is subse- quently fetched, the updated information is obtained ... QEMU already has support for this in the common code; enable it for s390x. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230807114921.438881-1-iii@linux.ibm.com> Acked-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-08-31Merge tag 'pull-target-arm-20230831' of ↵Stefan Hajnoczi
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Some of the preliminary patches for Cortex-A710 support * i.MX7 and i.MX6UL refactoring * Implement SRC device for i.MX7 * Catch illegal-exception-return from EL3 with bad NSE/NS * Use 64-bit offsets for holding time_t differences in RTC devices * Model correct number of MPU regions for an505, an521, an524 boards # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmTwbukZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3ihBD/wK8Iz0KpTAwZBDAodnSZrh # tQnJAvYFp8CxA4O8sZ9IeWsZh90gzsTCZi0NqUTTzvWCJfxkB7qTPdlJT5IzVxou # oEUk2aogSJhRA3XRJzqArXsPlnZGSYDbtwKx4VtfCvOCCH08Y7nhnFaRj1oFnR4Q # 0PE/8YtGXTBxLHrO8U3tomg7zElzOUP8ZVZtb30BOyw1jtfSD03IZR8dzpA43u1E # Hh418WvVekmwFoFNh8yUeHzbyXMZufzvbJPuDGJ8pPWwIpvSG6chOnKF8jZll+Ur # DqOsDkGlQgcBR2QwYfSPClrEkX8yahJ95PBfM6giG+DQC7OiElqXqTiUGZcpgUVo # uSUbzS4YPsxCnyVV6SBXV+f/8hdXBxOSHTgl7OAFa8X9OwWwspxHJ/v2o/2ibnUT # hTTkFp/w1nQwVEN8xf1DOUpm/J2Wr8UeH4f776daSrfKAol2BKbHb8dOgGLQCwqb # G+iDcE4bkzRqly6f+uVk8xSEZDd9P1NYoxKV+gNlV1dTspdHVpTC+rXMa8dRw5hI # 4KgaAslj++Xa229xkjORXCJ1cICRIebYg7+SjvTtGBYsFV7plsCcYb/R9yLmhVCf # fKHKKaYe9sQJ82apOIkTc+nnW8BQQx6XUmU/A//iZ8JGLk6DpJcZ8f1m/2rVZTsl # 9+lsmpBf4w+uR4o+Womhfw== # =MFh3 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 31 Aug 2023 06:43:53 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20230831' of https://git.linaro.org/people/pmaydell/qemu-arm: (24 commits) hw/arm: Set number of MPU regions correctly for an505, an521, an524 hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init rtc: Use time_t for passing and returning time offsets hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm() target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS Add i.MX7 SRC device implementation Add i.MX7 missing TZ devices and memory regions Refactor i.MX7 processor code Add i.MX6UL missing devices. Refactor i.MX6UL processor code Remove i.MX7 IOMUX GPR device from i.MX6UL target/arm: properly document FEAT_CRC32 target/arm: Implement FEAT_HPDS2 as a no-op target/arm: Suppress FEAT_TRBE (Trace Buffer Extension) target/arm: Apply access checks to neoverse-v1 special registers target/arm: Apply access checks to neoverse-n1 special registers target/arm: Introduce make_ccsidr64 ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-08-31target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_initPeter Maydell
Where architecturally one ARM_FEATURE_X flag implies another ARM_FEATURE_Y, we allow the CPU init function to only set X, and then set Y for it. Currently we do this in two places -- we set a few flags in arm_cpu_post_init() because we need them to decide which properties to create on the CPU object, and then we do the rest in arm_cpu_realizefn(). However, this is fragile, because it's easy to add a new property and not notice that this means that an X-implies-Y check now has to move from realize to post-init. As a specific example, the pmsav7-dregion property is conditional on ARM_FEATURE_PMSA && ARM_FEATURE_V7, which means it won't appear on the Cortex-M33 and -M55, because they set ARM_FEATURE_V8 and rely on V8-implies-V7, which doesn't happen until the realizefn. Move all of these X-implies-Y checks into a new function, which we call at the top of arm_cpu_post_init(), so the feature bits are available at that point. This does now give us the reverse issue, that if there's a feature bit which is enabled or disabled by the setting of a property then then X-implies-Y features that are dependent on that property need to be in realize, not in this new function. But the only one of those is the "EL3 implies VBAR" which is already in the right place, so putting things this way round seems better to me. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230724174335.2150499-2-peter.maydell@linaro.org
2023-08-31target/arm: Catch illegal-exception-return from EL3 with bad NSE/NSPeter Maydell
The architecture requires (R_TYTWB) that an attempt to return from EL3 when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This enforces that the CPU can't ever be executing below EL3 with the NSE,NS bits indicating an invalid security state.) We were missing this check; add it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230807150618.101357-1-peter.maydell@linaro.org
2023-08-31target/arm: properly document FEAT_CRC32Alex Bennée
This is a mandatory feature for Armv8.1 architectures but we don't state the feature clearly in our emulation list. Also include FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org Cc: qemu-stable@nongnu.org Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org> [PMM: pluralize 'instructions' in docs] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-08-31target/arm: Implement FEAT_HPDS2 as a no-opRichard Henderson
This feature allows the operating system to set TCR_ELx.HWU* to allow the implementation to use the PBHA bits from the block and page descriptors for for IMPLEMENTATION DEFINED purposes. Since QEMU has no need to use these bits, we may simply ignore them. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230811214031.171020-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-08-31target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)Richard Henderson
Like FEAT_TRF (Self-hosted Trace Extension), suppress tracing external to the cpu, which is out of scope for QEMU. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230811214031.171020-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-08-31target/arm: Apply access checks to neoverse-v1 special registersRichard Henderson
There is only one additional EL1 register modeled, which also needs to use access_actlr_w. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230811214031.171020-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-08-31target/arm: Apply access checks to neoverse-n1 special registersRichard Henderson
Access to many of the special registers is enabled or disabled by ACTLR_EL[23], which we implement as constant 0, which means that all writes outside EL3 should trap. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230811214031.171020-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-08-31target/arm: Introduce make_ccsidr64Richard Henderson
Do not hard-code the constants for Neoverse V1. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230811214031.171020-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-08-31target/arm: When tag memory is not present, set MTE=1Richard Henderson
When the cpu support MTE, but the system does not, reduce cpu support to user instructions at EL0 instead of completely disabling MTE. If we encounter a cpu implementation which does something else, we can revisit this setting. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230811214031.171020-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-08-31target/arm: Support more GM blocksizesRichard Henderson
Support all of the easy GM block sizes. Use direct memory operations, since the pointers are aligned. While BS=2 (16 bytes, 1 tag) is a legal setting, that requires an atomic store of one nibble. This is not difficult, but there is also no point in supporting it until required. Note that cortex-a710 sets GM blocksize to match its cacheline size of 64 bytes. I expect many implementations will also match the cacheline, which makes 16 bytes very unlikely. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230811214031.171020-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-08-31target/arm: Allow cpu to configure GM blocksizeRichard Henderson
Previously we hard-coded the blocksize with GMID_EL1_BS. But the value we choose for -cpu max does not match the value that cortex-a710 uses. Mirror the way we handle dcz_blocksize. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230811214031.171020-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-08-31target/arm: Reduce dcz_blocksize to uint8_tRichard Henderson
This value is only 4 bits wide. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230811214031.171020-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-08-30gdbstub: replace global gdb_has_xml with a functionAlex Bennée
Try and make the self reported global hack a little less hackish by providing a query function instead. As gdb_has_xml was always set if we negotiated XML we can now use the presence of ->target_xml as the test instead. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230829161528.2707696-12-alex.bennee@linaro.org>
2023-08-28Merge tag 'pull-tcg-20230823-2' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi
accel/*: Widen pc/saved_insn for *_sw_breakpoint accel/tcg: Replace remaining target_ulong in system-mode accel tcg: spelling fixes tcg: Document bswap, hswap, wswap byte patterns tcg: Introduce negsetcond opcodes tcg: Fold deposit with zero to and tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32 tcg/i386: Drop BYTEH deposits for 64-bit tcg/i386: Allow immediate as input to deposit target/*: Use tcg_gen_negsetcond_* # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmTnoP4dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV80MAf+NCEN7bwqGWmWGtfz # YGXp6J51rDwOWVVzTZDv2Gtkc4/Cv0wwtLk4JT5Sg/LQur3tie/bgqOY1SBb4cRq # UC1ERk3oqvmh8+aUqCc2SsncVtBduxAMqdlIhuD886SuZHgdry5cp2/MaOEFL/Un # yQoKl238OzTmIuKnf4p/NnfD4PZxEtzKy9vQyHKswDH5f2+egaqpmKOL/6Xtl8rL # 2nXPbd1UTlMu/QLlQ/CLKcW3Z9eBNrYDSQV1+K2J5ZjSFey8H5RUv3UAfqRpY00b # EObcNCMSc6D9bpb2p34QENZNh9GiHE9Stg9VGNFOGilaaMxoa6yowlgz9Dz9xlWN # OHG1ug== # =ed8f # -----END PGP SIGNATURE----- # gpg: Signature made Thu 24 Aug 2023 14:27:10 EDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20230823-2' of https://gitlab.com/rth7680/qemu: (48 commits) tcg: spelling fixes docs/devel/tcg-ops: fix missing newlines in "Host vector operations" target/cris: Fix a typo in gen_swapr() tcg/tcg-op: Document wswap_i64() byte pattern tcg/tcg-op: Document hswap_i32/64() byte pattern tcg/tcg-op: Document bswap64_i64() byte pattern tcg/tcg-op: Document bswap32_i64() byte pattern tcg/tcg-op: Document bswap32_i32() byte pattern tcg/tcg-op: Document bswap16_i64() byte pattern tcg/tcg-op: Document bswap16_i32() byte pattern tcg/i386: Implement negsetcond_* tcg/i386: Use shift in tcg_out_setcond tcg/i386: Clear dest first in tcg_out_setcond if possible tcg/i386: Use CMP+SBB in tcg_out_setcond tcg/i386: Merge tcg_out_movcond{32,64} tcg/i386: Merge tcg_out_setcond{32,64} tcg/i386: Merge tcg_out_brcond{32,64} tcg/sparc64: Implement negsetcond_* tcg/s390x: Implement negsetcond_* tcg/riscv: Implement negsetcond_* ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-08-28Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi
* separate accepted and auto-installed versions of Python dependencies * bump tricore container to Debian 11 * small configure cleanups # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmTsZ14UHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroMlVQf+Juomqo/luBwWwwguEZp32s+c+CYI # HZJJJSIycq/VY2OsT9e+H1eMJYsCsdzJxn1NcnmEIUSMRkIuCxV5F62gaMl6BjgF # tH8v4y1ZBDc0i0zw6qkuZM4sydNkK1XohGeOp8NkTE7F2fX0DT2AO17rSKIHh77R # enNE5yq+s0YGHfYz7PbNvT1G+YXqt9SEEfCqIHkCQccjgFx9PEJu7PPuWdIYLG5s # VVIyrbZzcX7OmQCCWdEZCe5t8swbOHtzE5D3JUVvfnUDj3BONXQybp/14rEikrjU # fuy9sf3qW4XlwzPOUWFlPfxJIg8KWB1fL2wIppDn2gKrBB7fekwz5hlJRA== # =lZmw # -----END PGP SIGNATURE----- # gpg: Signature made Mon 28 Aug 2023 05:22:38 EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: configure: remove unnecessary mkdir -p configure: fix container_hosts misspellings and duplications target/i386: add support for VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE tests/docker: add python3-tomli dependency to containers Revert "tests: Use separate virtual environment for avocado" configure: switch to ensuregroup python: use vendored tomli configure: never use PyPI for Meson lcitool: bump libvirt-ci submodule and regenerate python: mkvenv: add ensuregroup command python: mkvenv: introduce TOML-like representation of dependencies python: mkvenv: tweak the matching of --diagnose to depspecs dockerfiles: bump tricore cross compiler container to Debian 11 configure: fix and complete detection of tricore tools Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-08-28Merge tag 'devel-hppa-priv-cleanup2-pull-request' of ↵Stefan Hajnoczi
https://github.com/hdeller/qemu-hppa into staging target/hppa: Clean up conversion from/to MMU index and privilege level Make the conversion between privilege level and QEMU MMU index consistent, and afterwards switch to MMU indices 11-15. Signed-off-by: Helge Deller <deller@gmx.de> # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCZOtpFAAKCRD3ErUQojoP # X0lxAPwKfsMZOO/e81XXLgxeEZ5R4yjtIelErvOWmMvBfxEDUwEA6HgJt4gOe1uR # Dw7d+wTqr+CSOj5I87+sJYl1FmihzQU= # =01eA # -----END PGP SIGNATURE----- # gpg: Signature made Sun 27 Aug 2023 11:17:40 EDT # gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F # gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown] # gpg: aka "Helge Deller <deller@kernel.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603 # Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F * tag 'devel-hppa-priv-cleanup2-pull-request' of https://github.com/hdeller/qemu-hppa: target/hppa: Switch to use MMU indices 11-15 target/hppa: Use privilege helper in hppa_get_physical_address() target/hppa: Do not use hardcoded value for tlb_flush_*() target/hppa: Add privilege to MMU index conversion helpers target/hppa: Add missing PL1 and PL2 privilege levels Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-08-28target/i386: add support for VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSEAke Koomsin
Current QEMU can expose waitpkg to guests when it is available. However, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE is still not recognized and masked by QEMU. This can lead to an unexpected situation when a L1 hypervisor wants to expose waitpkg to a L2 guest. The L1 hypervisor can assume that VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE exists as waitpkg is available. The L1 hypervisor then can accidentally expose waitpkg to the L2 guest. This will cause invalid opcode exception in the L2 guest when it executes waitpkg related instructions. This patch adds VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE support, and sets up dependency between the bit and CPUID_7_0_ECX_WAITPKG. QEMU should not expose waitpkg feature if VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE is not available to avoid unexpected invalid opcode exception in L2 guests. Signed-off-by: Ake Koomsin <ake@igel.co.jp> Message-ID: <20230807093339.32091-2-ake@igel.co.jp> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-08-27target/hppa: Switch to use MMU indices 11-15Helge Deller
The MMU indices 9-15 will use shorter assembler instructions when run on a x86-64 host. So, switch over to those to get smaller code and maybe minimally faster emulation. Signed-off-by: Helge Deller <deller@gmx.de>
2023-08-25target/hppa: Use privilege helper in hppa_get_physical_address()Helge Deller
Convert hppa_get_physical_address() to use the privilege helper macro. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-08-25target/hppa: Do not use hardcoded value for tlb_flush_*()Helge Deller
Avoid using hardcoded values when calling the tlb_flush*() functions. Instead, define and use HPPA_MMU_FLUSH_MASK (keeping the current behavior, which doesn't flush the physical address MMU). Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-08-25target/hppa: Add privilege to MMU index conversion helpersHelge Deller
Add two macros which convert privilege level to/from MMU index: - PRIV_TO_MMU_IDX(priv) returns the MMU index for the given privilege level - MMU_IDX_TO_PRIV(mmu_idx) returns the corresponding privilege level for this MMU index The introduction of those macros make the code easier to read and will help to improve performance in follow-up patch. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-08-25target/hppa: Add missing PL1 and PL2 privilege levelsHelge Deller
The hppa CPU has 4 privilege levels (0-3). Mention the missing PL1 and PL2 levels, although the Linux kernel uses only 0 (KERNEL) and 3 (USER). Not sure about HP-UX. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-08-24target/cris: Fix a typo in gen_swapr()Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230823145542.79633-9-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-08-24target/tricore: Replace gen_cond_w with tcg_gen_negsetcond_tlRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-08-24target/sparc: Use tcg_gen_movcond_i64 in gen_edgeRichard Henderson
The setcond + neg + or sequence is a complex method of performing a conditional move. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-08-24target/ppc: Use tcg_gen_negsetcond_*Richard Henderson
Tested-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-08-24target/openrisc: Use tcg_gen_negsetcond_*Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-08-24target/m68k: Use tcg_gen_negsetcond_*Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-08-24target/arm: Use tcg_gen_negsetcond_*Richard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-08-24target/alpha: Use tcg_gen_movcond_i64 in gen_fold_mzeroRichard Henderson
The setcond + neg + and sequence is a complex method of performing a conditional move. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-08-24target/m68k: Use tcg_gen_deposit_i32 in gen_partset_regRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-08-24include/exec: Replace target_ulong with abi_ptr in cpu_[st|ld]*()Anton Johansson
Changes the address type of the guest memory read/write functions from target_ulong to abi_ptr. (abi_ptr is currently typedef'd to target_ulong but that will change in a following commit.) This will reduce the coupling between accel/ and target/. Note: Function pointers that point to cpu_[st|ld]*() in target/riscv and target/rx are also updated in this commit. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230807155706.9580-6-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-08-24sysemu/hvf: Use vaddr for hvf_arch_[insert|remove]_hw_breakpointAnton Johansson
Changes the signature of the target-defined functions for inserting/removing hvf hw breakpoints. The address and length arguments are now of vaddr type, which both matches the type used internally in accel/hvf/hvf-all.c and makes the api target-agnostic. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230807155706.9580-5-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-16 21:29:34 +0000