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2023-11-06target/hppa: Clear upper bits in mtctl for pa1.xHelge Deller
Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Avoid async_safe_run_on_cpu on uniprocessor systemRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Add pa2.0 cpu local tlb flushesHelge Deller
The previous decoding misnamed the bit it called "local". Other than the name, the implementation was correct for pa1.x. Rename this field to "tlbe". PA2.0 adds (a real) local bit to PxTLB, and also adds a range of pages to flush in GR[b]. Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement pa2.0 data prefetch instructionsRichard Henderson
These are aliased onto the normal integer loads to %g0. Since we don't emulate caches, prefetch is a nop. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Return zero for r0 from load_gprRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Precompute zero into DisasContextRichard Henderson
Reduce the number of times we look for the constant 0. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Fix interruption based on default PSWHelge Deller
The default PSW is set by the operating system with the PDC_PSW firmware call. Use that setting to decide if wide mode is to be enabled for interruptions and EIRR usage. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement PERMHRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement MIXH, MIXWRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HSHLADD, HSHRADDRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HSHL, HSHRRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HAVGRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HSUBRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HADDRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64Richard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Use tcg_temp_new_i64 not tcg_temp_newRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Adjust vmstate_env for pa2.0 tlbRichard Henderson
Split out the tlb to a subsection so that it can be separately versioned -- the format is only partially following the architecture and is partially guided by the qemu implementation. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove remaining TARGET_REGISTER_BITS redirectionsRichard Henderson
The conversions to/from i64 can be eliminated entirely, folding computation into adjacent operations. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove most of the TARGET_REGISTER_BITS redirectionsRichard Henderson
Remove all but those intended to change type to or from i64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove TARGET_REGISTER_BITSRichard Henderson
Rely only on TARGET_LONG_BITS, fixed at 64, and hppa_is_pa20. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement IDTLBT, IITLBTRichard Henderson
Rename the existing insert tlb helpers to emphasize that they are for pa1.1 cpus. Implement a combined i/d tlb for pa2.0. Still missing is the new 'P' tlb bit. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement STDBYRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOMRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement SHRPDRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement EXTRDRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement DEPD, DEPDIRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement LDD, LDCD, LDDA, STD, STDARichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode ADDB double-wordRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode CMPIB double-wordRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for cmpb instructionsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for bb instructionsRichard Henderson
Manipulate the shift count so that the bit to be tested is always placed at the MSB. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for sub instructionsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for add instructionsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for cmpclr instructionsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for unit instructionsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for logical instructionsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove TARGET_HPPA64Richard Henderson
Allow both user-only and system mode to run pa2.0 cpus. Avoid creating a separate qemu-system-hppa64 binary; force the qemu-hppa binary to use TARGET_ABI32. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Drop attempted gdbstub support for hppa64Richard Henderson
There is no support for hppa64 in gdb. Any attempt to provide the data for the larger hppa64 registers results in an error from gdb. Mask CR_SAR writes to the width of the register: 5 or 6 bits. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Pass d to do_unit_condRichard Henderson
Hoist the resolution of d up one level above do_unit_cond. All computations are logical, and are simplified by using a mask of the correct width, after which the result may be compared with zero. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Pass d to do_sed_condRichard Henderson
Hoist the resolution of d up one level above do_sed_cond. The MOVB comparison and the existing shift/extract/deposit are all 32-bit. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Pass d to do_log_condRichard Henderson
Hoist the resolution of d up one level above do_log_cond. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Pass d to do_sub_condRichard Henderson
Hoist the resolution of d up one level above do_sub_cond. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Pass d to do_condRichard Henderson
Hoist the resolution of d up one level above do_cond. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: sar register allows only 5 bits on 32-bit CPUHelge Deller
The sar shift amount register is limited to 5 bits when running a 32-bit CPU. Strip off the remaining bits. The interesting part is, that this register allows to detect at runtime if a physical CPU is capable to execute PA2.0 (64-bit) instructions. Signed-off-by: Helge Deller <deller@gmx.de>
2023-11-06target/hppa: Mask inputs in copy_iaoq_entryRichard Henderson
Ensure that the destination is always a valid GVA offset. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Use copy_iaoq_entry for link in do_ibranchRichard Henderson
We need to make sure the link is masked properly along the use_nullify_skip path. The other three settings of a link register already use this. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb]Richard Henderson
This will be how we ensure that the IAOQ is always valid per PSW.W, therefore all stores to these two variables must be done with this function. Use third argument -1 if the destination is always dynamic, and fourth argument NULL if the destination is always static. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Pass DisasContext to copy_iaoq_entryRichard Henderson
Interface change only, no functional effect. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Fix hppa64 addressingRichard Henderson
In form_gva and cpu_get_tb_cpu_state, we must truncate when PSW_W == 0. In space_select, the bits that choose the space depend on PSW_W. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Adjust hppa_cpu_dump_state for hppa64Richard Henderson
Dump all 64 bits for pa2.0 and low 32 bits for pa1.x. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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