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2023-10-27target/arm: Move feature test functions to their own headerPeter Maydell
The feature test functions isar_feature_*() now take up nearly a thousand lines in target/arm/cpu.h. This header file is included by a lot of source files, most of which don't need these functions. Move the feature test functions to their own header file. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-2-peter.maydell@linaro.org
2023-10-27target/arm: Implement Neoverse N2 CPU modelPeter Maydell
Implement a model of the Neoverse N2 CPU. This is an Armv9.0-A processor very similar to the Cortex-A710. The differences are: * no FEAT_EVT * FEAT_DGH (data gathering hint) * FEAT_NV (not yet implemented in QEMU) * Statistical Profiling Extension (not implemented in QEMU) * 48 bit physical address range, not 40 * CTR_EL0.DIC = 1 (no explicit icache cleaning needed) * PMCR_EL0.N = 6 (always 6 PMU counters, not 20) Because it has 48-bit physical address support, we can use this CPU in the sbsa-ref board as well as the virt board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20230915185453.1871167-3-peter.maydell@linaro.org
2023-10-27target/arm: Correct minor errors in Cortex-A710 definitionPeter Maydell
Correct a couple of minor errors in the Cortex-A710 definition: * ID_AA64DFR0_EL1.DebugVer is 9 (indicating Armv8.4 debug architecture) * ID_AA64ISAR1_EL1.APA is 5 (indicating more PAuth support) * there is an IMPDEF CPUCFR_EL1, like that on the Neoverse-N1 Fixes: e3d45c0a89576 ("target/arm: Implement cortex-a710") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20230915185453.1871167-2-peter.maydell@linaro.org
2023-10-27Merge tag 'pull-sp-20231025' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi
Convert target/sparc to decodetree. # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmU5ruAdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9NWQgAjkWxZi9Je3yWR0x0 # mQmlx0zlyjK4PeMGS14mr0mxFAqvC5gFHNzw0WtLaVw9gyfm6EKXwervtm9mCg7F # PPQzF9IqSoKqGV2fFlWpVWmUPmKNhLY5hS7Pvampg8Tkt6X6NJQdbaUpEQW6U47I # C4/AAygaj6fd99BEZI36A2oxg6D0HM9cV1LUm43e+yQ1KCQaTO+3u8oDZA8MkXu1 # p2bxPXazClLe+ywwtR9tp28IgQszQ10NxECzhJ34ezLCbTreH//ycpPI2h8Xskdc # lDkCu3OJa8aIalGOpDL71Qemp9KfRYkOyPlahAZx3haZC24fnVvVRoMiV8Z5+iYk # gq2VnA== # =/gf2 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 26 Oct 2023 09:12:16 JST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-sp-20231025' of https://gitlab.com/rth7680/qemu: (94 commits) target/sparc: Remove disas_sparc_legacy target/sparc: Convert FZERO, FONE to decodetree target/sparc: Move FPACK16, FPACKFIX to decodetree target/sparc: Move FPCMP* to decodetree target/sparc: Convert FCMP, FCMPE to decodetree target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree target/sparc: Move FMOVq, FNEGq, FABSq to decodetree target/sparc: Move FdTOq, FxTOq to decodetree target/sparc: Move FiTOq, FsTOq to decodetree target/sparc: Move FqTOd, FqTOx to decodetree target/sparc: Move FqTOs, FqTOi to decodetree target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree target/sparc: Move gen_fop_FD insns to decodetree target/sparc: Move FDMULQ to decodetree target/sparc: Move FSMULD to decodetree target/sparc: Move gen_fop_QQQ insns to decodetree target/sparc: Move gen_fop_DDD insns to decodetree target/sparc: Move gen_fop_FFF insns to decodetree target/sparc: Move FSQRTq to decodetree target/sparc: Move gen_fop_DD insns to decodetree ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-25kvm: i8254: require KVM_CAP_PIT2 and KVM_CAP_PIT_STATE2Paolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: i386: require KVM_CAP_SET_IDENTITY_MAP_ADDRPaolo Bonzini
This was introduced in KVM in Linux 2.6.32, we can require it unconditionally. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: i386: require KVM_CAP_ADJUST_CLOCKPaolo Bonzini
This was introduced in KVM in Linux 2.6.33, we can require it unconditionally. KVM_CLOCK_TSC_STABLE was only added in Linux 4.9, for now do not require it (though it would allow the removal of some pretty yucky code). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: i386: require KVM_CAP_MCEPaolo Bonzini
This was introduced in KVM in Linux 2.6.34, we can require it unconditionally. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: i386: require KVM_CAP_SET_VCPU_EVENTS and KVM_CAP_X86_ROBUST_SINGLESTEPPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: i386: require KVM_CAP_XSAVEPaolo Bonzini
This was introduced in KVM in Linux 2.6.36, and could already be used at the time to save/restore FPU data even on older processor. We can require it unconditionally and stop using KVM_GET/SET_FPU. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: i386: require KVM_CAP_DEBUGREGSPaolo Bonzini
This was introduced in KVM in Linux 2.6.35, we can require it unconditionally. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: i386: move KVM_CAP_IRQ_ROUTING detection to kvm_arch_required_capabilitiesPaolo Bonzini
Simple code cleanup. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: require KVM_IRQFD for kernel irqchipPaolo Bonzini
KVM_IRQFD was introduced in Linux 2.6.32, and since then it has always been available on architectures that support an in-kernel interrupt controller. We can require it unconditionally. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: require KVM_CAP_SIGNAL_MSIPaolo Bonzini
This was introduced in KVM in Linux 3.5, we can require it unconditionally in kvm_irqchip_send_msi(). However, not all architectures have to implement it so check it only in x86, the only architecture that ever had MSI injection but not KVM_CAP_SIGNAL_MSI. ARM uses it to detect the presence of the ITS emulation in the kernel, introduced in Linux 4.8. Assume that it's there and possibly fail when realizing the arm-its-kvm device. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25target/i386: check CPUID_PAE to determine 36 bit processor address spaceAni Sinha
PAE mode in x86 supports 36 bit address space. Check the PAE CPUID on the guest processor and set phys_bits to 36 if PAE feature is set. This is in addition to checking the presence of PSE36 CPUID feature for setting 36 bit phys_bits. Signed-off-by: Ani Sinha <anisinha@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-ID: <20230912120650.371781-1-anisinha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25target/i386: validate VEX.W for AVX instructionsPaolo Bonzini
Instructions in VEX exception class 6 generally look at the value of VEX.W. Note that the manual places some instructions incorrectly in class 4, for example VPERMQ which has no non-VEX encoding and no legacy SSE analogue. AMD does a mess of its own, as documented in the comment that this patch adds. Most of them are checked for VEX.W=0, and are listed in the manual (though with an omission) in table 2-16; VPERMQ and VPERMPD check for VEX.W=1, which is only listed in the instruction description. Others, such as VPSRLV, VPSLLV and the FMA3 instructions, use VEX.W to switch between a 32-bit and 64-bit operation. Fix more of the class 4/class 6 mismatches, and implement the check for VEX.W in TCG. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25target/i386: group common checks in the decoding phasePaolo Bonzini
In preparation for adding more similar checks, move the VEX.L=0 check and several X86_SPECIAL_* checks to a new field, where each bit represent a common check on unused bits, or a restriction on the processor mode. Likewise, many SVM intercepts can be checked during the decoding phase, the main exception being the selective CR0 write, MSR and IOIO intercepts. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25target/i386: implement SHA instructionsPaolo Bonzini
The implementation was validated with OpenSSL and with the test vectors in https://github.com/rust-lang/stdarch/blob/master/crates/core_arch/src/x86/sha.rs. The instructions provide a ~25% improvement on hashing a 64 MiB file: runtime goes down from 1.8 seconds to 1.4 seconds; instruction count on the host goes down from 5.8 billion to 4.8 billion with slightly better IPC too. Good job Intel. ;) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25target/sparc: Remove disas_sparc_legacyRichard Henderson
All instructions are now converted. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Convert FZERO, FONE to decodetreeRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move FPACK16, FPACKFIX to decodetreeRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move FPCMP* to decodetreeRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Convert FCMP, FCMPE to decodetreeRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetreeRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move FMOVq, FNEGq, FABSq to decodetreeRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move FdTOq, FxTOq to decodetreeRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move FiTOq, FsTOq to decodetreeRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move FqTOd, FqTOx to decodetreeRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move FqTOs, FqTOi to decodetreeRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move FiTOd, FsTOd, FsTOx to decodetreeRichard Henderson
Note that gen_ne_fop_DF was incorrectly named and does pass env. The two sets of helpers should have been unified. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move gen_fop_FD insns to decodetreeRichard Henderson
Move FdTOs, FdTOi, FxTOs. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move FDMULQ to decodetreeRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move FSMULD to decodetreeRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move gen_fop_QQQ insns to decodetreeRichard Henderson
Move FADDq, FSUBq, FMULq, FDIVq. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move gen_fop_DDD insns to decodetreeRichard Henderson
Move FADDd, FSUBd, FMULd, FDIVd. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move gen_fop_FFF insns to decodetreeRichard Henderson
Move FADDs, FSUBs, FMULs, FDIVs. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move FSQRTq to decodetreeRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move gen_fop_DD insns to decodetreeRichard Henderson
Move FSQRTd, FxTOd, FdTOx. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move gen_fop_FF insns to decodetreeRichard Henderson
Move FSQRTs, FiTOs, FsTOi. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move gen_gsr_fop_DDD insns to decodetreeRichard Henderson
Move FPACK32, FALIGNDATA, BSHUFFLE. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move PDIST to decodetreeRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move gen_ne_fop_DDD insns to decodetreeRichard Henderson
Move FMUL8x16, FMUL8x16AU, FMUL8x16AL, FMUL8SUx16, FMUL8ULx16, FMULD8SUx16, FMULD8ULx16, FPMERGE, FEXPAND, FANDNOT1d, FANDNOT2d, FANDd, FNANDd, FNORd, FORNOT1d, FORNOT2d, FORd, FPADD16d, FPADD32d, FPSUB16d, FPSUB32d, FXNORd, FXORd. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move gen_ne_fop_FFF insns to decodetreeRichard Henderson
Move FANDNOT1s, FANDNOT2s, FANDs, FNANDs, FNORs, FORNOT1s, FORNOT2s, FORs, FPADD16s, FPADD32s, FPSUB16s, FPSUB32s, FXNORs, FXORs. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Use tcg_gen_vec_{add,sub}*Richard Henderson
Replace the local helpers for the same integer operations. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D to decodetreeRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S to decodetreeRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move BMASK to decodetreeRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move ADDRALIGN* to decodetreeRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move ARRAY* to decodetreeRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move EDGE* to decodetreeRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-17 05:07:30 +0000