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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Split out the tlb to a subsection so that it can be separately
versioned -- the format is only partially following the architecture
and is partially guided by the qemu implementation.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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The conversions to/from i64 can be eliminated entirely,
folding computation into adjacent operations.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Remove all but those intended to change type to or from i64.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Rely only on TARGET_LONG_BITS, fixed at 64, and hppa_is_pa20.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Rename the existing insert tlb helpers to emphasize that they
are for pa1.1 cpus. Implement a combined i/d tlb for pa2.0.
Still missing is the new 'P' tlb bit.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Manipulate the shift count so that the bit to be tested
is always placed at the MSB.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Allow both user-only and system mode to run pa2.0 cpus.
Avoid creating a separate qemu-system-hppa64 binary;
force the qemu-hppa binary to use TARGET_ABI32.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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There is no support for hppa64 in gdb. Any attempt to provide the
data for the larger hppa64 registers results in an error from gdb.
Mask CR_SAR writes to the width of the register: 5 or 6 bits.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Hoist the resolution of d up one level above do_unit_cond.
All computations are logical, and are simplified by using a mask of the
correct width, after which the result may be compared with zero.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Hoist the resolution of d up one level above do_sed_cond.
The MOVB comparison and the existing shift/extract/deposit
are all 32-bit.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Hoist the resolution of d up one level above do_log_cond.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Hoist the resolution of d up one level above do_sub_cond.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Hoist the resolution of d up one level above do_cond.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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The sar shift amount register is limited to 5 bits when running
a 32-bit CPU. Strip off the remaining bits.
The interesting part is, that this register allows to detect at runtime
if a physical CPU is capable to execute PA2.0 (64-bit) instructions.
Signed-off-by: Helge Deller <deller@gmx.de>
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Ensure that the destination is always a valid GVA offset.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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We need to make sure the link is masked properly along the
use_nullify_skip path. The other three settings of a link
register already use this.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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This will be how we ensure that the IAOQ is always
valid per PSW.W, therefore all stores to these two
variables must be done with this function.
Use third argument -1 if the destination is always dynamic,
and fourth argument NULL if the destination is always static.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Interface change only, no functional effect.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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In form_gva and cpu_get_tb_cpu_state, we must truncate when PSW_W == 0.
In space_select, the bits that choose the space depend on PSW_W.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Dump all 64 bits for pa2.0 and low 32 bits for pa1.x.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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With pa2.0, absolute addresses are not the same as physical addresses,
and undergo a transformation based on PSW_W.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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With 64-bit registers, there are 16 carry bits in the PSW.
Clear reserved bits based on cpu revision.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Depend on hppa_is_pa20.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Prepare for the qemu binary supporting both pa10 and pa20
at the same time.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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These are 32-bit operations regardless of processor.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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