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2023-05-05target/riscv: Remove check on RVH for riscv_cpu_virt_enabledWeiwei Li
Since env->virt.VIRT_ONOFF is initialized as false, and will not be set to true when RVH is disabled, so we can just return this bit(false) when RVH is not disabled. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230327080858.39703-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Remove redundant check on RVHWeiwei Li
Check on riscv_cpu_virt_enabled contains the check on RVH. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230327080858.39703-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Remove redundant call to riscv_cpu_virt_enabledWeiwei Li
The assignment is done under the condition riscv_cpu_virt_enabled()=true. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230327080858.39703-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Fix itrigger when icount is usedLIU Zhiwei
When I boot a ubuntu image, QEMU output a "Bad icount read" message and exit. The reason is that when execute helper_mret or helper_sret, it will cause a call to icount_get_raw_locked (), which needs set can_do_io flag on cpustate. Thus we setting this flag when execute these two instructions. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230324064011.976-1-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Add support for ZceWeiwei Li
Add and expose property for Zce: * Specifying Zce without F includes Zca, Zcb, Zcmp, Zcmt. * Specifying Zce with F includes Zca, Zcb, Zcmp, Zcmt and Zcf. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-11-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: expose properties for Zc* extensionWeiwei Li
Expose zca,zcb,zcf,zcd,zcmp,zcmt properties. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-9-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: add support for Zcmt extensionWeiwei Li
Add encode, trans* functions and helper functions support for Zcmt instrutions. Add support for jvt csr. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-8-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: add support for Zcmp extensionWeiwei Li
Add encode, trans* functions for Zcmp instructions. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-7-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: add support for Zcb extensionWeiwei Li
Add encode and trans* functions support for Zcb instructions. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-6-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: add support for Zcd extensionWeiwei Li
Separate c_fld/c_fsd from fld/fsd to add additional check for c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse their encodings. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: add support for Zcf extensionWeiwei Li
Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: add support for Zca extensionWeiwei Li
Modify the check for C extension to Zca (C implies Zca). Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Message-Id: <20230307081403.61950-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: add cfg properties for Zc* extensionWeiwei Li
Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension. Add check for these properties. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: fix invalid riscv,event-to-mhpmcounters entryConor Dooley
dt-validate complains: > soc: pmu: {'riscv,event-to-mhpmcounters': > [[1, 1, 524281], [2, 2, 524284], [65561, 65561, 524280], > [65563, 65563, 524280], [65569, 65569, 524280], [0, 0, 0], [0, 0]], > pmu: riscv,event-to-mhpmcounters:6: [0, 0] is too short There are bogus 0 entries added at the end, of which one is of insufficient length. This happens because only 15 of fdt_event_ctr_map[]'s 20 elements are populated & qemu_fdt_setprop() is called using the size of the array. Reduce the array to 15 elements to make the error go away. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230404173333.35179-1-conor@kernel.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: redirect XVentanaCondOps to use the Zicond functionsPhilipp Tomsich
The Zicond standard extension implements the same instruction semantics as XVentanaCondOps, although using different mnemonics and opcodes. Point XVentanaCondOps to the (newly implemented) Zicond implementation to reduce the future maintenance burden. Also updating MAINTAINERS as trans_xventanacondops.c.inc. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307180708.302867-3-philipp.tomsich@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: refactor Zicond supportPhilipp Tomsich
After the original Zicond support was stuck/fell through the cracks on the mailing list at v3 (and a different implementation was merged in the meanwhile), we need to refactor Zicond to prepare it to be reused by XVentanaCondOps. This commit lifts the common logic out into gen_czero and uses this via gen_logic and 2 helper functions (effectively partial closures). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307180708.302867-2-philipp.tomsich@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Simplify arguments for riscv_csrrw_checkWeiwei Li
Remove RISCVCPU argument, and get cfg infomation from CPURISCVState directly. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230309071329.45932-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Simplify type conversion for CPURISCVStateWeiwei Li
Use CPURISCVState as argument directly in riscv_cpu_update_mip and riscv_timer_write_timecmp, since type converts from CPURISCVState to RISCVCPU in many caller of them and then back to CPURISCVState in them. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230309071329.45932-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Simplify getting RISCVCPU pointer from envWeiwei Li
Use env_archcpu() to get RISCVCPU pointer from env directly. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230309071329.45932-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Fix priv version dependency for vector and zfhLIU Zhiwei
Vector implicitly enables zve64d, zve64f, zve32f sub extensions. As vector only requires PRIV_1_10_0, these sub extensions should not require priv version higher than that. The same for Zfh. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20230321043415.754-1-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Avoid env_archcpu() when reading RISCVCPUConfigWeiwei Li
Use riscv_cpu_cfg(env) instead of env_archcpu().cfg. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230309071329.45932-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-02target/arm: Add compile time asserts to load/store_cpu_field macrosPeter Maydell
Add some compile-time asserts to the load_cpu_field() and store_cpu_field() macros that the struct field being accessed is the expected size. This lets us catch cases where we incorrectly tried to do a 32-bit load from a 64-bit struct field. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230424153909.1419369-3-peter.maydell@linaro.org
2023-05-02target/arm: Define and use new load_cpu_field_low32()Peter Maydell
In several places in the 32-bit Arm translate.c, we try to use load_cpu_field() to load from a CPUARMState field into a TCGv_i32 where the field is actually 64-bit. This works on little-endian hosts, but gives the wrong half of the register on big-endian. Add a new load_cpu_field_low32() which loads the low 32 bits of a 64-bit field into a TCGv_i32. The new macro includes a compile-time check against accidentally using it on a field of the wrong size. Use it to fix the two places in the code where we were using load_cpu_field() on a 64-bit field. This fixes a bug where on big-endian hosts the guest would crash after executing an ERET instruction, and a more corner case one where some UNDEFs for attempted accesses to MSR banked registers from Secure EL1 might go to the wrong EL. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230424153909.1419369-2-peter.maydell@linaro.org
2023-05-02arm/Kconfig: Always select SEMIHOSTING when TCG is presentFabiano Rosas
We are about to enable the build without TCG, so CONFIG_SEMIHOSTING and CONFIG_ARM_COMPATIBLE_SEMIHOSTING cannot be unconditionally set in default.mak anymore. So reflect the change in a Kconfig. Instead of using semihosting/Kconfig, use a target-specific file, so that the change doesn't affect other architectures which might implement semihosting in a way compatible with KVM. The selection from ARM_v7M needs to be removed to avoid a cycle during parsing. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230426180013.14814-11-farosas@suse.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-05-02target/arm: move cpu_tcg to tcg/cpu32.cClaudio Fontana
move the module containing cpu models definitions for 32bit TCG-only CPUs to tcg/ and rename it for clarity. Signed-off-by: Claudio Fontana <cfontana@suse.de> Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230426180013.14814-8-farosas@suse.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-05-02target/arm: Move 64-bit TCG CPUs into tcg/Fabiano Rosas
Move the 64-bit CPUs that are TCG-only: - cortex-a35 - cortex-a55 - cortex-a72 - cortex-a76 - a64fx - neoverse-n1 Keep the CPUs that can be used with KVM: - cortex-a57 - cortex-a53 - max - host Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230426180013.14814-6-farosas@suse.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-05-02target/arm: Do not expose all -cpu max features to qtestsFabiano Rosas
We're about to move the TCG-only -cpu max configuration code under CONFIG_TCG. To be able to do that we need to make sure the qtests still have some cpu configured even when no other accelerator is available. Delineate now what is used with TCG-only and what is also used with qtests to make the subsequent patches cleaner. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230426180013.14814-5-farosas@suse.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-05-02target/arm: Extract TCG -cpu max code into a functionFabiano Rosas
Introduce aarch64_max_tcg_initfn that contains the TCG-only part of -cpu max configuration. We'll need that to be able to restrict this code to a TCG-only config in the next patches. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fabiano Rosas <farosas@suse.de> Message-id: 20230426180013.14814-4-farosas@suse.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-05-02target/arm: Remove dead code from cpu_max_set_sve_max_vqFabiano Rosas
The sve-max-vq property has been removed from the -cpu max used with KVM, so code under kvm_enabled in cpu_max_set_sve_max_vq is not reachable. Fixes: 0baa21be49 ("target/arm: Make KVM -cpu max exactly like -cpu host") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fabiano Rosas <farosas@suse.de> Message-id: 20230426180013.14814-3-farosas@suse.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-05-02target/arm: Move cortex sysregs into a separate fileFabiano Rosas
The file cpu_tcg.c is about to be moved into the tcg/ directory, so move the register definitions into a new file. Also move the function declaration to the more appropriate cpregs.h. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230426180013.14814-2-farosas@suse.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-04-29Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson
* Fix compilation issues under Debian 10 * Update kernel headers to 6.3rc5 * Suppress GCC13 false positive in aio_bh_poll() * Add new x86 feature bits * Coverity fixes * More steps towards removing qatomic_mb_set/read * Fix reduced-phys-bits value for AMD SEV # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmRNC0IUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroNo0wgArWNGKZpbmQ0e5L6ajMvaaPmg4mVL # a2SJGU0TwTp0fUgZr14z2iwzIpSqQrsqhzTIAzOTs0OICDBPBuNvnRucMa+SVQGO # Tc89YAwBVDo66dAKhWi+WR9tx7sTFCso0nbsBfczzdnwAw3g1MJ87Ueqc5tlPGBK # E7YSAD6l4UuogoN5BLU7bSsG/X7bwcyzeUXRB4ik+Z9abWd4DH9qiROnBKLMmBLK # nAi47h8b8MltWORpO+wf6HtkMKi37SAzl9VLHVuHcRhIdY/JhWCRhYSo0HXhgX66 # JLVkyxFpIndT0dUW/xnqATGez92FRZyTxHbxbAcWM0SoC1jOVfUXB+7Gdw== # =vxou # -----END PGP SIGNATURE----- # gpg: Signature made Sat 29 Apr 2023 01:19:14 PM BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [undefined] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: cpus-common: stop using mb_set/mb_read async: Suppress GCC13 false positive in aio_bh_poll() tests: vhost-user-test: release mutex on protocol violation Update linux headers to v6.3rc5 update-linux-headers.sh: Add missing kernel headers. Fix libvhost-user.c compilation. target/i386: Add support for PREFETCHIT0/1 in CPUID enumeration target/i386: Add support for AVX-NE-CONVERT in CPUID enumeration target/i386: Add support for AVX-VNNI-INT8 in CPUID enumeration target/i386: Add support for AVX-IFMA in CPUID enumeration target/i386: Add support for AMX-FP16 in CPUID enumeration target/i386: Add support for CMPCCXADD in CPUID enumeration i386/cpu: Update how the EBX register of CPUID 0x8000001F is set i386/sev: Update checks and information related to reduced-phys-bits qemu-options.hx: Update the reduced-phys-bits documentation qapi, i386/sev: Change the reduced-phys-bits value from 5 to 1 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-04-28target/i386: Add support for PREFETCHIT0/1 in CPUID enumerationJiaxi Chen
Latest Intel platform Granite Rapids has introduced a new instruction - PREFETCHIT0/1, which moves code to memory (cache) closer to the processor depending on specific hints. The bit definition: CPUID.(EAX=7,ECX=1):EDX[bit 14] Add CPUID definition for PREFETCHIT0/1. Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com> Signed-off-by: Tao Su <tao1.su@linux.intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-Id: <20230303065913.1246327-7-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-04-28target/i386: Add support for AVX-NE-CONVERT in CPUID enumerationJiaxi Chen
AVX-NE-CONVERT is a new set of instructions which can convert low precision floating point like BF16/FP16 to high precision floating point FP32, as well as convert FP32 elements to BF16. This instruction allows the platform to have improved AI capabilities and better compatibility. The bit definition: CPUID.(EAX=7,ECX=1):EDX[bit 5] Add CPUID definition for AVX-NE-CONVERT. Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com> Signed-off-by: Tao Su <tao1.su@linux.intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-Id: <20230303065913.1246327-6-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-04-28target/i386: Add support for AVX-VNNI-INT8 in CPUID enumerationJiaxi Chen
AVX-VNNI-INT8 is a new set of instructions in the latest Intel platform Sierra Forest, aims for the platform to have superior AI capabilities. This instruction multiplies the individual bytes of two unsigned or unsigned source operands, then adds and accumulates the results into the destination dword element size operand. The bit definition: CPUID.(EAX=7,ECX=1):EDX[bit 4] AVX-VNNI-INT8 is on a new feature bits leaf. Add a CPUID feature word FEAT_7_1_EDX for this leaf. Add CPUID definition for AVX-VNNI-INT8. Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com> Signed-off-by: Tao Su <tao1.su@linux.intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-Id: <20230303065913.1246327-5-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-04-28target/i386: Add support for AVX-IFMA in CPUID enumerationJiaxi Chen
AVX-IFMA is a new instruction in the latest Intel platform Sierra Forest. This instruction packed multiplies unsigned 52-bit integers and adds the low/high 52-bit products to Qword Accumulators. The bit definition: CPUID.(EAX=7,ECX=1):EAX[bit 23] Add CPUID definition for AVX-IFMA. Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com> Signed-off-by: Tao Su <tao1.su@linux.intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-Id: <20230303065913.1246327-4-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-04-28target/i386: Add support for AMX-FP16 in CPUID enumerationJiaxi Chen
Latest Intel platform Granite Rapids has introduced a new instruction - AMX-FP16, which performs dot-products of two FP16 tiles and accumulates the results into a packed single precision tile. AMX-FP16 adds FP16 capability and allows a FP16 GPU trained model to run faster without loss of accuracy or added SW overhead. The bit definition: CPUID.(EAX=7,ECX=1):EAX[bit 21] Add CPUID definition for AMX-FP16. Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com> Signed-off-by: Tao Su <tao1.su@linux.intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-Id: <20230303065913.1246327-3-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-04-28target/i386: Add support for CMPCCXADD in CPUID enumerationJiaxi Chen
CMPccXADD is a new set of instructions in the latest Intel platform Sierra Forest. This new instruction set includes a semaphore operation that can compare and add the operands if condition is met, which can improve database performance. The bit definition: CPUID.(EAX=7,ECX=1):EAX[bit 7] Add CPUID definition for CMPCCXADD. Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com> Signed-off-by: Tao Su <tao1.su@linux.intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-Id: <20230303065913.1246327-2-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-04-28i386/cpu: Update how the EBX register of CPUID 0x8000001F is setTom Lendacky
Update the setting of CPUID 0x8000001F EBX to clearly document the ranges associated with fields being set. Fixes: 6cb8f2a663 ("cpu/i386: populate CPUID 0x8000_001F when SEV is active") Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <5822fd7d02b575121380e1f493a8f6d9eba2b11a.1664550870.git.thomas.lendacky@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-04-28i386/sev: Update checks and information related to reduced-phys-bitsTom Lendacky
The value of the reduced-phys-bits parameter is propogated to the CPUID information exposed to the guest. Update the current validation check to account for the size of the CPUID field (6-bits), ensuring the value is in the range of 1 to 63. Maintain backward compatibility, to an extent, by allowing a value greater than 1 (so that the previously documented value of 5 still works), but not allowing anything over 63. Fixes: d8575c6c02 ("sev/i386: add command to initialize the memory encryption context") Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <cca5341a95ac73f904e6300f10b04f9c62e4e8ff.1664550870.git.thomas.lendacky@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-04-28s390x/gdb: Split s390-virt.xmlIlya Leoshkevich
Both TCG and KVM emulate ckc, cputm, last_break and prefix, and it's quite useful to have them during debugging. Right now they are grouped together with KVM-only pp, pfault_token, pfault_select and pfault_compare in s390-virt.xml, and are not available when debugging TCG-emulated code. Move KVM-only registers into the new s390-virt-kvm.xml file. Advertise s390-virt.xml always, and the new s390-virt-kvm.xml only for KVM. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230314101813.174874-1-iii@linux.ibm.com> Acked-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-04-23tcg: Replace tcg_abort with g_assert_not_reachedRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-04-22Merge tag 'pull-hex-20230421' of https://github.com/quic/qemu into stagingRichard Henderson
Hexagon update # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEENjXHiM5iuR/UxZq0ewJE+xLeRCIFAmRCu/gACgkQewJE+xLe # RCIlnQgAkdLjTQGC+V+HKIcuD6BWCqk+fRuMAI7Ban/bq/bN5nm4xv8rWIdBAKkj # xj1MxWgW/yns76A/OupC6tJD/1PvkdvCGUPIdRphK60raP3l1o88ivs2WsJdw9/O # PAubqwyYNhdnEIhiA9QOVkUoh7rVVKzpri2ldRNdmxBc9tQi9POYvKSVy6rSoiQw # rhrYfpc0fd50L4oeT1rqpCad9NrbDlCwrRSc/1oA/pUPiuxUYYr6BiIx0ytbTvH2 # aMJUdA2ynkrgxkFn3v42qOrT7M9cs1b7abHz9obWibl6Jqcl4AIoKvF/kAuDmQuV # FAq8Qhn/cK49M9xCEZOI8olE/xIUjQ== # =+I8i # -----END PGP SIGNATURE----- # gpg: Signature made Fri 21 Apr 2023 05:38:16 PM BST # gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422 * tag 'pull-hex-20230421' of https://github.com/quic/qemu: Hexagon (target/hexagon) Add overrides for cache/sync/barrier instructions Hexagon (target/hexagon) Remove unused slot variable in helpers Hexagon (tests/tcg/hexagon) Move HVX test infra to header file Hexagon (target/hexagon) Updates to USR should use get_result_gpr Hexagon (target/hexagon) Add overrides for count trailing zeros/ones Hexagon (target/hexagon) Merge arguments to probe_pkt_scalar_hvx_stores Hexagon (target/hexagon) Remove redundant/unused macros Use black code style for python scripts Use f-strings in python scripts Hexagon (translate.c): avoid redundant PC updates on COF Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-04-22Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson
* Optional use of Meson wrap for slirp * Coverity fixes * Avoid -Werror=maybe-uninitialized * Mark coroutine QMP command functions as coroutine_fn * Mark functions that suspend as coroutine_mixed_fn * target/i386: Fix SGX CPUID leaf * First batch of qatomic_mb_read() removal * Small atomic.rst improvement * NBD cleanup * Update libvirt-ci submodule # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmRBAzwUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroP64gf+NzLW95tylCfhKuuLq/TjuOTQqHCD # KVLlA1I3pwJfk4SUuigrnaJtwfa/tBiWxfaivUdPAzPzeXyxcVSOps0neohrmFBh # 2e3ylBWWz22K0gkLtrFwJT99TVy6w6Xhj9SX8HPRfxl4k8yMPrUJNW78hh6APAwq # /etZY6+ieHC7cwG4xluhxsHnxnBYBYD+18hUd+b5LchD/yvCSCNNiursutpa0Ar/ # r/HtDwNFKlaApO3sU4R3yYgdS1Fvcas4tDZaumADsQlSG5z+UeJldc98LiRlFrAA # gnskBSaaly/NgWqY3hVCYaBGyjD4lWPkX/FEChi0XX6Fl1P0umQAv/7z3w== # =XSAs # -----END PGP SIGNATURE----- # gpg: Signature made Thu 20 Apr 2023 10:17:48 AM BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [undefined] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (25 commits) tests: lcitool: Switch to OpenSUSE Leap 15.4 tests: libvirt-ci: Update to commit '2fa24dce8bc' configure: Honour cross-prefix when finding ObjC compiler coverity: unify Fedora dockerfiles nbd: a BlockExport always has a BlockBackend docs: explain effect of smp_read_barrier_depends() on modern architectures qemu-coroutine: remove qatomic_mb_read() postcopy-ram: do not use qatomic_mb_read block-backend: remove qatomic_mb_read() target/i386: Change wrong XFRM value in SGX CPUID leaf monitor: mark mixed functions that can suspend migration: mark mixed functions that can suspend io: mark mixed functions that can suspend qapi-gen: mark coroutine QMP command functions as coroutine_fn target/mips: tcg: detect out-of-bounds accesses to cpu_gpr and cpu_gpr_hi coverity: update COMPONENTS.md lasi: fix RTC migration target/i386: Avoid unreachable variable declaration in mmu_translate() configure: Avoid -Werror=maybe-uninitialized tests: bios-tables-test: replace memset with initializer ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-04-21Hexagon (target/hexagon) Add overrides for cache/sync/barrier instructionsTaylor Simpson
Most of these are not modelled in QEMU, so save the overhead of calling a helper. The only exception is dczeroa. It assigns to hex_dczero_addr, which is handled during packet commit. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230410202402.2856852-1-tsimpson@quicinc.com>
2023-04-21Hexagon (target/hexagon) Remove unused slot variable in helpersTaylor Simpson
The slot variable in helpers was only passed to log_reg_write function where the argument is unused. - Remove declaration from generated helper functions - Remove slot argument from log_reg_write Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230407204521.357244-1-tsimpson@quicinc.com>
2023-04-21Hexagon (target/hexagon) Updates to USR should use get_result_gprTaylor Simpson
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230405164211.30015-3-tsimpson@quicinc.com>
2023-04-21Hexagon (target/hexagon) Add overrides for count trailing zeros/onesTaylor Simpson
The following instructions are overriden S2_ct0 Count trailing zeros S2_ct1 Count trailing ones S2_ct0p Count trailing zeros (register pair) S2_ct1p Count trailing ones (register pair) These instructions are not handled by idef-parser because the imported semantics uses bit-reverse. However, they are straightforward to implement in TCG with tcg_gen_ctzi_* Test cases added to tests/tcg/hexagon/misc.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230405164211.30015-1-tsimpson@quicinc.com>
2023-04-21Hexagon (target/hexagon) Merge arguments to probe_pkt_scalar_hvx_storesTaylor Simpson
Reducing the number of arguments reduces the overhead of the helper call Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230405164211.30015-2-tsimpson@quicinc.com>
2023-04-21Hexagon (target/hexagon) Remove redundant/unused macrosTaylor Simpson
Remove the following macros (remnants of the old generator design) READ_REG READ_PREG WRITE_RREG WRITE_PREG Modify macros that rely on the above The following are unused READ_IREG fGET_FIELD fSET_FIELD fREAD_P3 fREAD_NPC fWRITE_LC0 fWRITE_LC1 Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230405183048.147767-1-tsimpson@quicinc.com>
2023-04-21Use black code style for python scriptsMarco Liebel
Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Acked-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20230320092533.2859433-3-quic_mliebel@quicinc.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-18 08:16:07 +0000