aboutsummaryrefslogtreecommitdiff
path: root/target
AgeCommit message (Expand)Author
2023-05-05target/riscv: Remove check on RVH for riscv_cpu_virt_enabledWeiwei Li
2023-05-05target/riscv: Remove redundant check on RVHWeiwei Li
2023-05-05target/riscv: Remove redundant call to riscv_cpu_virt_enabledWeiwei Li
2023-05-05target/riscv: Fix itrigger when icount is usedLIU Zhiwei
2023-05-05target/riscv: Add support for ZceWeiwei Li
2023-05-05target/riscv: expose properties for Zc* extensionWeiwei Li
2023-05-05target/riscv: add support for Zcmt extensionWeiwei Li
2023-05-05target/riscv: add support for Zcmp extensionWeiwei Li
2023-05-05target/riscv: add support for Zcb extensionWeiwei Li
2023-05-05target/riscv: add support for Zcd extensionWeiwei Li
2023-05-05target/riscv: add support for Zcf extensionWeiwei Li
2023-05-05target/riscv: add support for Zca extensionWeiwei Li
2023-05-05target/riscv: add cfg properties for Zc* extensionWeiwei Li
2023-05-05target/riscv: fix invalid riscv,event-to-mhpmcounters entryConor Dooley
2023-05-05target/riscv: redirect XVentanaCondOps to use the Zicond functionsPhilipp Tomsich
2023-05-05target/riscv: refactor Zicond supportPhilipp Tomsich
2023-05-05target/riscv: Simplify arguments for riscv_csrrw_checkWeiwei Li
2023-05-05target/riscv: Simplify type conversion for CPURISCVStateWeiwei Li
2023-05-05target/riscv: Simplify getting RISCVCPU pointer from envWeiwei Li
2023-05-05target/riscv: Fix priv version dependency for vector and zfhLIU Zhiwei
2023-05-05target/riscv: Avoid env_archcpu() when reading RISCVCPUConfigWeiwei Li
2023-05-02target/arm: Add compile time asserts to load/store_cpu_field macrosPeter Maydell
2023-05-02target/arm: Define and use new load_cpu_field_low32()Peter Maydell
2023-05-02arm/Kconfig: Always select SEMIHOSTING when TCG is presentFabiano Rosas
2023-05-02target/arm: move cpu_tcg to tcg/cpu32.cClaudio Fontana
2023-05-02target/arm: Move 64-bit TCG CPUs into tcg/Fabiano Rosas
2023-05-02target/arm: Do not expose all -cpu max features to qtestsFabiano Rosas
2023-05-02target/arm: Extract TCG -cpu max code into a functionFabiano Rosas
2023-05-02target/arm: Remove dead code from cpu_max_set_sve_max_vqFabiano Rosas
2023-05-02target/arm: Move cortex sysregs into a separate fileFabiano Rosas
2023-04-29Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson
2023-04-28target/i386: Add support for PREFETCHIT0/1 in CPUID enumerationJiaxi Chen
2023-04-28target/i386: Add support for AVX-NE-CONVERT in CPUID enumerationJiaxi Chen
2023-04-28target/i386: Add support for AVX-VNNI-INT8 in CPUID enumerationJiaxi Chen
2023-04-28target/i386: Add support for AVX-IFMA in CPUID enumerationJiaxi Chen
2023-04-28target/i386: Add support for AMX-FP16 in CPUID enumerationJiaxi Chen
2023-04-28target/i386: Add support for CMPCCXADD in CPUID enumerationJiaxi Chen
2023-04-28i386/cpu: Update how the EBX register of CPUID 0x8000001F is setTom Lendacky
2023-04-28i386/sev: Update checks and information related to reduced-phys-bitsTom Lendacky
2023-04-28s390x/gdb: Split s390-virt.xmlIlya Leoshkevich
2023-04-23tcg: Replace tcg_abort with g_assert_not_reachedRichard Henderson
2023-04-22Merge tag 'pull-hex-20230421' of https://github.com/quic/qemu into stagingRichard Henderson
2023-04-22Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson
2023-04-21Hexagon (target/hexagon) Add overrides for cache/sync/barrier instructionsTaylor Simpson
2023-04-21Hexagon (target/hexagon) Remove unused slot variable in helpersTaylor Simpson
2023-04-21Hexagon (target/hexagon) Updates to USR should use get_result_gprTaylor Simpson
2023-04-21Hexagon (target/hexagon) Add overrides for count trailing zeros/onesTaylor Simpson
2023-04-21Hexagon (target/hexagon) Merge arguments to probe_pkt_scalar_hvx_storesTaylor Simpson
2023-04-21Hexagon (target/hexagon) Remove redundant/unused macrosTaylor Simpson
2023-04-21Use black code style for python scriptsMarco Liebel