slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2023-06-16	target/loongarch: Fix CSR.DMW0-3.VSEG check	Jiajie Chen
2023-06-16	hw/intc: Set physical cpuid route for LoongArch ipi device	Tianrui Zhao
2023-06-15	target/arm: Allow users to set the number of VFP registers	Cédric Le Goater
2023-06-14	Merge tag 'pull-riscv-to-apply-20230614' of https://github.com/alistair23/qem...	Richard Henderson
2023-06-13	target/i386: Rename helper template headers as '.h.inc'	Philippe Mathieu-Daudé
2023-06-13	target/i386/helper: Shuffle do_cpu_init()	Philippe Mathieu-Daudé
2023-06-13	target/i386/helper: Remove do_cpu_sipi() stub for user-mode emulation	Philippe Mathieu-Daudé
2023-06-13	target/hppa/meson: Only build int_helper.o with system emulation	Philippe Mathieu-Daudé
2023-06-13	target/riscv: Smepmp: Return error when access permission not allowed in PMP	Himanshu Chauhan
2023-06-13	target/riscv/vector_helper.c: Remove the check for extra tail elements	Xiao Wang
2023-06-13	target/riscv/vector_helper.c: clean up reference of MTYPE	Xiao Wang
2023-06-13	target/riscv: Fix initialized value for cur_pmmask	Weiwei Li
2023-06-13	target/riscv: Remove pc_succ_insn from DisasContext	Weiwei Li
2023-06-13	target/riscv: Enable PC-relative translation	Weiwei Li
2023-06-13	target/riscv: Use true diff for gen_pc_plus_diff	Weiwei Li
2023-06-13	target/riscv: Change gen_set_pc_imm to gen_update_pc	Weiwei Li
2023-06-13	target/riscv: Change gen_goto_tb to work on displacements	Weiwei Li
2023-06-13	target/riscv: Introduce cur_insn_len into DisasContext	Weiwei Li
2023-06-13	target/riscv: Fix target address to update badaddr	Weiwei Li
2023-06-13	target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info	Weiwei Li
2023-06-13	target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h	Weiwei Li
2023-06-13	target/riscv: smstateen knobs	Mayuresh Chitale
2023-06-13	target/riscv: Reuse tb->flags.FS	Mayuresh Chitale
2023-06-13	target/riscv: smstateen check for fcsr	Mayuresh Chitale
2023-06-13	target/riscv: Update cur_pmmask/base when xl changes	Weiwei Li
2023-06-13	target/riscv: Fix pointer mask transformation for vector address	Weiwei Li
2023-06-13	target/riscv: Deny access if access is partially inside the PMP entry	Weiwei Li
2023-06-13	target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write	Weiwei Li
2023-06-13	target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes	Weiwei Li
2023-06-13	target/riscv: Flush TLB when pmpaddr is updated	Weiwei Li
2023-06-13	target/riscv: Update the next rule addr in pmpaddr_csr_write()	Weiwei Li
2023-06-13	target/riscv: Flush TLB when MMWP or MML bits are changed	Weiwei Li
2023-06-13	target/riscv: Remove unused paramters in pmp_hart_has_privs_default()	Weiwei Li
2023-06-13	target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled	Weiwei Li
2023-06-13	target/riscv: Change the return type of pmp_hart_has_privs() to bool	Weiwei Li
2023-06-13	target/riscv: Make the short cut really work in pmp_hart_has_privs	Weiwei Li
2023-06-13	target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp	Weiwei Li
2023-06-13	target/riscv: Update pmp_get_tlb_size()	Weiwei Li
2023-06-13	target/riscv: rework write_misa()	Daniel Henrique Barboza
2023-06-13	target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()	Daniel Henrique Barboza
2023-06-13	target/riscv/cpu.c: validate extensions before riscv_timer_init()	Daniel Henrique Barboza
2023-06-13	target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()	Daniel Henrique Barboza
2023-06-13	target/riscv/cpu.c: add priv_spec validate/disable_exts helpers	Daniel Henrique Barboza
2023-06-13	target/riscv: Update check for Zca/Zcf/Zcd	Weiwei Li
2023-06-13	target/riscv: Mask the implicitly enabled extensions in isa_string based on p...	Weiwei Li
2023-06-13	target/riscv: add PRIV_VERSION_LATEST	Daniel Henrique Barboza
2023-06-13	target/riscv/cpu.c: remove set_priv_version()	Daniel Henrique Barboza
2023-06-13	target/riscv/cpu.c: remove set_vext_version()	Daniel Henrique Barboza
2023-06-13	target/riscv/cpu.c: add riscv_cpu_validate_v()	Daniel Henrique Barboza
2023-06-13	target/riscv: Move zc* out of the experimental properties	Weiwei Li