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AgeCommit message (Expand)Author
2022-01-29Merge remote-tracking branch 'remotes/quintela-gitlab/tags/migration-20220128...Peter Maydell
2022-01-28Remove unnecessary minimum_version_id_old fieldsPeter Maydell
2022-01-28target/arm: Use correct entrypoint for SVC taken from Hyp to HypPeter Maydell
2022-01-28target/arm: Log CPU index in 'Taking exception' logPeter Maydell
2022-01-21target/riscv: Relax UXL field for debuggingLIU Zhiwei
2022-01-21target/riscv: Enable uxl field writeLIU Zhiwei
2022-01-21target/riscv: Set default XLEN for hypervisorLIU Zhiwei
2022-01-21target/riscv: Adjust scalar reg in vector with XLENLIU Zhiwei
2022-01-21target/riscv: Adjust vector address with maskLIU Zhiwei
2022-01-21target/riscv: Fix check range for first fault onlyLIU Zhiwei
2022-01-21target/riscv: Remove VILL field in VTYPELIU Zhiwei
2022-01-21target/riscv: Adjust vsetvl according to XLENLIU Zhiwei
2022-01-21target/riscv: Split out the vill from vtypeLIU Zhiwei
2022-01-21target/riscv: Split pm_enabled into mask and baseLIU Zhiwei
2022-01-21target/riscv: Calculate address according to XLENLIU Zhiwei
2022-01-21target/riscv: Alloc tcg global for cur_pm[mask|base]LIU Zhiwei
2022-01-21target/riscv: Create current pm fields in envLIU Zhiwei
2022-01-21target/riscv: Adjust csr write mask with XLENLIU Zhiwei
2022-01-21target/riscv: Relax debug check for pm writeLIU Zhiwei
2022-01-21target/riscv: Use gdb xml according to max mxlenLIU Zhiwei
2022-01-21target/riscv: Extend pc for runtime pc writeLIU Zhiwei
2022-01-21target/riscv: Ignore the pc bits above XLENLIU Zhiwei
2022-01-21target/riscv: Create xl field in envLIU Zhiwei
2022-01-21target/riscv: Sign extend pc for different XLENLIU Zhiwei
2022-01-21target/riscv: Sign extend link reg for jal and jalrLIU Zhiwei
2022-01-21target/riscv: Don't save pc when exception returnLIU Zhiwei
2022-01-21target/riscv: Adjust pmpcfg access with mxlLIU Zhiwei
2022-01-21target/riscv: rvv-1.0: Allow Zve32f extension to be turned onFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for scalar fp insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for configuration insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang
2022-01-21target/riscv: rvv-1.0: Allow Zve64f extension to be turned onFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for scalar fp insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for load and store insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for configuration insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang
2022-01-21target/riscv: Support virtual time context synchronizationYifei Jiang
2022-01-21target/riscv: Implement virtual time adjusting with vm state changingYifei Jiang
2022-01-21target/riscv: Add kvm_riscv_get/put_regs_timerYifei Jiang
2022-01-21target/riscv: Add host cpu typeYifei Jiang
2022-01-21target/riscv: Handle KVM_EXIT_RISCV_SBI exitYifei Jiang
2022-01-21target/riscv: Support setting external interrupt by KVMYifei Jiang
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