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2021-01-29Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20210129-1' into staging target-arm queue: * Implement ID_PFR2 * Conditionalize DBGDIDR * rename xlnx-zcu102.canbusN properties * provide powerdown/reset mechanism for secure firmware on 'virt' board * hw/misc: Fix arith overflow in NPCM7XX PWM module * target/arm: Replace magic value by MMU_DATA_LOAD definition * configure: fix preadv errors on Catalina macOS with new XCode * Various configure and other cleanups in preparation for iOS support * hvf: Add hypervisor entitlement to output binaries (needed for Big Sur) * Implement pvpanic-pci device * Convert the CMSDK timer devices to the Clock framework # gpg: Signature made Fri 29 Jan 2021 16:08:02 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210129-1: (46 commits) hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS arm: Remove frq properties on CMSDK timer, dualtimer, watchdog, ARMSSE arm: Don't set freq properties on CMSDK timer, dualtimer, watchdog, ARMSSE hw/arm/armsse: Use Clock to set system_clock_scale tests/qtest/cmsdk-apb-watchdog-test: Test clock changes hw/watchdog/cmsdk-apb-watchdog: Convert to use Clock input hw/timer/cmsdk-apb-dualtimer: Convert to use Clock input hw/timer/cmsdk-apb-timer: Convert to use Clock input hw/arm/stellaris: Create Clock input for watchdog hw/arm/stellaris: Convert SSYS to QOM device hw/arm/musca: Create and connect ARMSSE Clocks hw/arm/mps2-tz: Create and connect ARMSSE Clocks hw/arm/mps2: Create and connect SYSCLK Clock hw/arm/mps2: Inline CMSDK_APB_TIMER creation hw/arm/armsse: Wire up clocks hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ" hw/watchdog/cmsdk-apb-watchdog: Add Clock input hw/timer/cmsdk-apb-dualtimer: Add Clock input hw/timer/cmsdk-apb-timer: Add Clock input hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-29target/arm: Replace magic value by MMU_DATA_LOAD definitionPhilippe Mathieu-Daudé
cpu_get_phys_page_debug() uses 'DATA LOAD' MMU access type. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210127232822.3530782-1-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-29target/arm: Conditionalize DBGDIDRRichard Henderson
Only define the register if it exists for the cpu. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210120031656.737646-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-29target/arm: Implement ID_PFR2Richard Henderson
This was defined at some point before ARMv8.4, and will shortly be used by new processor descriptions. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210120204400.1056582-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-29Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier2/tags/trivial-branch-for-6.0-pull-request' into staging Trivial patches 20210129 # gpg: Signature made Fri 29 Jan 2021 08:32:17 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-for-6.0-pull-request: target/rx: Fix compiler errors for build with sanitizers net/slirp.c: Fix spelling error in error message tcg/tci: Restrict tci_write_reg16() to 64-bit hosts MAINTAINERS: Update 9pfs tree URL Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-29target/rx: Fix compiler errors for build with sanitizersStefan Weil
gcc (Debian 10.2.1-6) 10.2.1 20210110 aborts builds with enabled sanitizers: ../../../target/rx/op_helper.c: In function ‘helper_scmpu’: ../../../target/rx/op_helper.c:213:24: error: ‘tmp1’ may be used uninitialized in this function [-Werror=maybe-uninitialized] 213 | env->psw_c = (tmp0 >= tmp1); | ~~~~~~^~~~~~~~ ../../../target/rx/op_helper.c:213:24: error: ‘tmp0’ may be used uninitialized in this function [-Werror=maybe-uninitialized] ../../../target/rx/op_helper.c: In function ‘helper_suntil’: ../../../target/rx/op_helper.c:299:23: error: ‘tmp’ may be used uninitialized in this function [-Werror=maybe-uninitialized] 299 | env->psw_c = (tmp <= env->regs[2]); | ~~~~~^~~~~~~~~~~~~~~~ ../../../target/rx/op_helper.c: In function ‘helper_swhile’: ../../../target/rx/op_helper.c:318:23: error: ‘tmp’ may be used uninitialized in this function [-Werror=maybe-uninitialized] 318 | env->psw_c = (tmp <= env->regs[2]); | ~~~~~^~~~~~~~~~~~~~~~ Rewriting the code fixes those errors. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210128172127.46041-1-sw@weilnetz.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-01-28qapi: Use QAPI_LIST_APPEND in trivial casesEric Blake
The easiest spots to use QAPI_LIST_APPEND are where we already have an obvious pointer to the tail of a list. While at it, consistently use the variable name 'tail' for that purpose. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210113221013.390592-5-eblake@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-01-27target/microblaze: Add security attributes on memory transactionsJoe Komlodi
Using the cfg.use_non_secure bitfield and the MMU access type, we can determine if the access should be secure or not. Signed-off-by: Joe Komlodi <komlodi@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <1611274735-303873-4-git-send-email-komlodi@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2021-01-27target/microblaze: use MMUAccessType instead of int in mmu_translateJoe Komlodi
Using MMUAccessType makes it more clear what the variable's use is. No functional change. Signed-off-by: Joe Komlodi <komlodi@xilinx.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <1611274735-303873-3-git-send-email-komlodi@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2021-01-27target/microblaze: Add use-non-secure propertyJoe Komlodi
This property is used to control the security of the following interfaces on MicroBlaze: M_AXI_DP - data interface M_AXI_IP - instruction interface M_AXI_DC - dcache interface M_AXI_IC - icache interface It works by enabling or disabling the use of the non_secure[3:0] signals. Interfaces and their corresponding values are taken from: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug984-vivado-microblaze-ref.pdf page 153. Signed-off-by: Joe Komlodi <komlodi@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <1611274735-303873-2-git-send-email-komlodi@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2021-01-23Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ↵Peter Maydell
staging * Make MinGW respect --bindir (Joshua) * Switch MinGW to a "deep" installation (Joshua + NSIS fixes by myself) * Fix compilation errors/warnings (Qixin, Philippe) * QemuOpts cleanups (myself) * Consistency improvements for -action (myself) * remove deprecated "change vnc TARGET" functionality (myself) * meson cleanups (Marc-André, Philippe, myself) * IDE out-of-bounds access (Prasad) * LA57 fix for -cpu max (Weijiang) # gpg: Signature made Sat 23 Jan 2021 20:55:59 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini-gitlab/tags/for-upstream: (30 commits) qemu-option: warn for short-form boolean options qemu-option: move help handling to get_opt_name_value qemu-option: clean up id vs. list->merge_lists vnc: support "-vnc help" qmp: remove deprecated "change" command hmp: remove "change vnc TARGET" command acceptance: switch to QMP change-vnc-password command meson.build: Detect bzip2 program meson.build: Declare global edk2_targets / install_edk2_blobs variables meson: Add a section header for library dependencies meson: Display crypto-related information altogether meson: Display block layer information altogether meson: Display accelerators and selected targets altogether meson: Summarize compilation-related information altogether meson: Summarize overall features altogether meson: Display host binaries information altogether meson: Summarize information related to directories first meson: convert wixl detection to Meson nsis: adjust for new MinGW paths meson: Declare have_virtfs_proxy_helper in main meson.build ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-21x86/cpu: Use max host physical address if -cpu max option is appliedYang Weijiang
QEMU option -cpu max(max_features) means "Enables all features supported by the accelerator in the current host", this looks true for all the features except guest max physical address width, so add this patch to enable it. Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> Message-Id: <20210113090430.26394-1-weijiang.yang@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-01-21s390x: Use strpadcpy for copying vm nameMiroslav Rezanina
Using strncpy with length equal to the size of target array, GCC 11 reports following warning: warning: '__builtin_strncpy' specified bound 256 equals destination size [-Wstringop-truncation] We can prevent this warning by using strpadcpy that copies string up to specified length, zeroes target array after copied string and does not raise warning when length is equal to target array size (and ending '\0' is discarded). Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <6f86915755219cf6a671788075da4809b57f7d7b.1610607906.git.mrezanin@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-01-21s390x/tcg: Ignore register content if b1/b2 is zero when handling EXECUTEDavid Hildenbrand
In our EXECUTE fast path, we have to ignore the content of r0, if specified by b1 or b2. Fixes: d376f123c7de ("target/s390x: Re-implement a few EXECUTE target insns directly") Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Nick Desaulniers <ndesaulniers@google.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210111163845.18148-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-01-21s390x/tcg: Don't ignore content in r0 when not specified via "b" or "x"David Hildenbrand
Using get_address() with register identifiers comming from an "r" field is wrong: if the "r" field designates "r0", we don't read the content and instead assume 0 - which should only be applied when the register was specified via "b" or "x". PoP 5-11 "Operand-Address Generation": "A zero in any of the B1, B2, X2, B3, or B4 fields indicates the absence of the corresponding address component. For the absent component, a zero is used in forming the intermediate sum, regardless of the contents of general register 0. A displacement of zero has no special significance." This BUG became visible for CSPG as generated by LLVM-12 in the upstream Linux kernel (v5.11-rc2), used while creating the linear mapping in vmem_map_init(): Trying to store to address 0 results in a Low Address Protection exception. Debugging this was more complicated than it could have been: The program interrupt handler in the kernel will try to crash the kernel: doing so, it will enable DAT. As the linear mapping is not created yet (asce=0), we run into an addressing exception while tring to walk non-existant DAT tables, resulting in a program exception loop. This allows for booting upstream Linux kernels compiled by clang-12. Most of these cases seem to be broken forever. Reported-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Nick Desaulniers <ndesaulniers@google.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Cc: Guenter Roeck <linux@roeck-us.net> Cc: Christian Borntraeger <borntraeger@de.ibm.com> Cc: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210111163845.18148-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-01-21s390x/tcg: Fix RISBHGDavid Hildenbrand
RISBHG is broken and currently hinders clang-11 builds of upstream kernels from booting: the kernel crashes early, while decompressing the image. [...] Kernel fault: interruption code 0005 ilc:2 Kernel random base: 0000000000000000 PSW : 0000200180000000 0000000000017a1e R:0 T:0 IO:0 EX:0 Key:0 M:0 W:0 P:0 AS:0 CC:2 PM:0 RI:0 EA:3 GPRS: 0000000000000001 0000000c00000000 00000003fffffff4 00000000fffffff0 0000000000000000 00000000fffffff4 000000000000000c 00000000fffffff0 00000000fffffffc 0000000000000000 00000000fffffff8 00000000008e25a8 0000000000000009 0000000000000002 0000000000000008 000000000000bce0 One example of a buggy instruction is: 17dde: ec 1e 00 9f 20 5d risbhg %r1,%r14,0,159,32 With %r14 = 0x9 and %r1 = 0x7 should result in %r1 = 0x900000007, however, results in %r1 = 0. Let's interpret values of i3/i4 as documented in the PoP and make computation of "mask" only based on i3 and i4 and use "pmask" only at the very end to make sure wrapping is only applied to the high/low doubleword. With this patch, I can successfully boot a v5.11-rc2 kernel built with clang-11, and gcc builds keep on working. Fixes: 2d6a869833d9 ("target-s390: Implement RISBG") Reported-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Nick Desaulniers <ndesaulniers@google.com> Cc: Guenter Roeck <linux@roeck-us.net> Cc: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210111163845.18148-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-01-21s390x/tcg: Fix ALGSIDavid Hildenbrand
Looks like something went wrong whiel touching that line. Instead of "r1" we need a new temporary. Also, we have to pass MO_TEQ, to indicate that we are working with 64-bit values. Let's revert these changes. Fixes: ff26d287bddc ("target/s390x: Improve cc computation for ADD LOGICAL") Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Nick Desaulniers <ndesaulniers@google.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210111163845.18148-2-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-01-19target/arm/m_helper: Silence GCC 10 maybe-uninitialized errorPhilippe Mathieu-Daudé
When building with GCC 10.2 configured with --extra-cflags=-Os, we get: target/arm/m_helper.c: In function ‘arm_v7m_cpu_do_interrupt’: target/arm/m_helper.c:1811:16: error: ‘restore_s16_s31’ may be used uninitialized in this function [-Werror=maybe-uninitialized] 1811 | if (restore_s16_s31) { | ^ target/arm/m_helper.c:1350:10: note: ‘restore_s16_s31’ was declared here 1350 | bool restore_s16_s31; | ^~~~~~~~~~~~~~~ cc1: all warnings being treated as errors Initialize the 'restore_s16_s31' variable to silence the warning. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210119062739.589049-1-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: Update REV, PUNPK for pred_descRichard Henderson
Update all users of do_perm_pred2 for the new predicate descriptor field definitions. Cc: qemu-stable@nongnu.org Buglink: https://bugs.launchpad.net/bugs/1908551 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210113062650.593824-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: Update ZIP, UZP, TRN for pred_descRichard Henderson
Update all users of do_perm_pred3 for the new predicate descriptor field definitions. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210113062650.593824-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: Update PFIRST, PNEXT for pred_descRichard Henderson
These two were odd, in that do_pfirst_pnext passed the count of 64-bit words rather than bytes. Change to pass the standard pred_full_reg_size to avoid confusion. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210113062650.593824-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: Introduce PREDDESC field definitionsRichard Henderson
SVE predicate operations cannot use the "usual" simd_desc encoding, because the lengths are not a multiple of 8. But we were abusing the SIMD_* fields to store values anyway. This abuse broke when SIMD_OPRSZ_BITS was modified in e2e7168a214. Introduce a new set of field definitions for exclusive use of predicates, so that it is obvious what kind of predicate we are manipulating. To be used in future patches. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210113062650.593824-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: refactor vae1_tlbmask()Rémi Denis-Courmont
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-19-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: enable Secure EL2 in max CPURémi Denis-Courmont
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-18-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: Implement SCR_EL2.EEL2Rémi Denis-Courmont
This adds handling for the SCR_EL3.EEL2 bit. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Message-id: 20210112104511.36576-17-remi.denis.courmont@huawei.com [PMM: Applied fixes for review issues noted by RTH: - check for FEATURE_AARCH64 before checking sel2 isar feature - correct the commit message subject line] Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: revector to run-time pick target ELRémi Denis-Courmont
On ARMv8-A, accesses by 32-bit secure EL1 to monitor registers trap to the upper (64-bit) EL. With Secure EL2 support, we can no longer assume that that is always EL3, so make room for the value to be computed at run-time. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-16-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: set HPFAR_EL2.NS on secure stage 2 faultsRémi Denis-Courmont
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-15-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: secure stage 2 translation regimeRémi Denis-Courmont
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-14-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: generalize 2-stage page-walk conditionRémi Denis-Courmont
The stage_1_mmu_idx() already effectively keeps track of which translation regimes have two stages. Don't hard-code another test. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-13-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: translate NS bit in page-walksRémi Denis-Courmont
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-12-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: do S1_ptw_translate() before address space lookupRémi Denis-Courmont
In the secure stage 2 translation regime, the VSTCR.SW and VTCR.NSW bits can invert the secure flag for pagetable walks. This patchset allows S1_ptw_translate() to change the non-secure bit. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-11-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: handle VMID change in secure stateRémi Denis-Courmont
The VTTBR write callback so far assumes that the underlying VM lies in non-secure state. This handles the secure state scenario. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-10-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: add ARMv8.4-SEL2 system registersRémi Denis-Courmont
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-9-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: add MMU stage 1 for Secure EL2Rémi Denis-Courmont
This adds the MMU indices for EL2 stage 1 in secure state. To keep code contained, which is largelly identical between secure and non-secure modes, the MMU indices are reassigned. The new assignments provide a systematic pattern with a non-secure bit. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-8-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: add 64-bit S-EL2 to EL exception tableRémi Denis-Courmont
With the ARMv8.4-SEL2 extension, EL2 is a legal exception level in secure mode, though it can only be AArch64. This patch adds the target EL for exceptions from 64-bit S-EL2. It also fixes the target EL to EL2 when HCR.{A,F,I}MO are set in secure mode. Those values were never used in practice as the effective value of HCR was always 0 in secure mode. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-7-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: Define isar_feature function to test for presence of SEL2Rémi Denis-Courmont
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-6-remi.denis.courmont@huawei.com [PMM: tweaked commit message to match reduced scope of patch following rebase] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: factor MDCR_EL2 common handlingRémi Denis-Courmont
This adds a common helper to compute the effective value of MDCR_EL2. That is the actual value if EL2 is enabled in the current security context, or 0 elsewise. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-5-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: use arm_hcr_el2_eff() where applicableRémi Denis-Courmont
This will simplify accessing HCR conditionally in secure state. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-4-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: use arm_is_el2_enabled() where applicableRémi Denis-Courmont
Do not assume that EL2 is available in and only in non-secure context. That equivalence is broken by ARMv8.4-SEL2. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-3-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: add arm_is_el2_enabled() helperRémi Denis-Courmont
This checks if EL2 is enabled (meaning EL2 registers take effects) in the current security context. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-2-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: remove redundant testsRémi Denis-Courmont
In this context, the HCR value is the effective value, and thus is zero in secure mode. The tests for HCR.{F,I}MO are sufficient. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-1-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: Use object_property_add_bool for "sve" propertyRichard Henderson
The interface for object_property_add_bool is simpler, making the code easier to understand. Reviewed-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210111235740.462469-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: Add cpu properties to control pauthRichard Henderson
The crypto overhead of emulating pauth can be significant for some workloads. Add two boolean properties that allows the feature to be turned off, on with the architected algorithm, or on with an implementation defined algorithm. We need two intermediate booleans to control the state while parsing properties lest we clobber ID_AA64ISAR1 into an invalid intermediate state. Tested-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210111235740.462469-3-richard.henderson@linaro.org [PMM: fixed docs typo, tweaked text to clarify that the impdef algorithm is specific to QEMU] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: Implement an IMPDEF pauth algorithmRichard Henderson
Without hardware acceleration, a cryptographically strong algorithm is too expensive for pauth_computepac. Even with hardware accel, we are not currently expecting to link the linux-user binaries to any crypto libraries, and doing so would generally make the --static build fail. So choose XXH64 as a reasonably quick and decent hash. Tested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210111235740.462469-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-18Merge remote-tracking branch ↵Peter Maydell
'remotes/stsquad/tags/pull-testing-and-misc-180121-2' into staging Testing, gdbstub and semihosting patches: - clean-ups to docker images - drop duplicate jobs from shippable - prettier tag generation (+gtags) - generate browsable source tree - more Travis->GitLab migrations - fix checkpatch to deal with commits - gate gdbstub tests on 8.3.1, expand tests - support Xfer:auxv:read gdb packet - better gdbstub cleanup - use GDB's SVE register layout - make arm-compat-semihosting common - add riscv semihosting support - add HEAPINFO, ELAPSED, TICKFREQ, TMPNAM and ISERROR to semihosting # gpg: Signature made Mon 18 Jan 2021 10:09:11 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-and-misc-180121-2: (30 commits) semihosting: Implement SYS_ISERROR semihosting: Implement SYS_TMPNAM semihosting: Implement SYS_ELAPSED and SYS_TICKFREQ riscv: Add semihosting support for user mode riscv: Add semihosting support semihosting: Support SYS_HEAPINFO when env->boot_info is not set semihosting: Change internal common-semi interfaces to use CPUState * semihosting: Change common-semi API to be architecture-independent semihosting: Move ARM semihosting code to shared directories target/arm: use official org.gnu.gdb.aarch64.sve layout for registers gdbstub: ensure we clean-up when terminated gdbstub: drop gdbserver_cleanup in favour of gdb_exit gdbstub: drop CPUEnv from gdb_exit() gdbstub: add support to Xfer:auxv:read: packet gdbstub: implement a softmmu based test Revert "tests/tcg/multiarch/Makefile.target: Disable run-gdbstub-sha1 test" configure: gate our use of GDB to 8.3.1 or above test/guest-debug: echo QEMU command as well scripts/checkpatch.pl: fix git-show invocation to include diffstat gitlab: migrate the minimal tools and unit tests from Travis ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # default-configs/targets/riscv32-linux-user.mak # default-configs/targets/riscv64-linux-user.mak
2021-01-18riscv: Add semihosting supportKeith Packard
Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210107170717.2098982-6-keithp@keithp.com> Message-Id: <20210108224256.2321-17-alex.bennee@linaro.org>
2021-01-18semihosting: Change common-semi API to be architecture-independentKeith Packard
The public API is now defined in hw/semihosting/common-semi.h. do_common_semihosting takes CPUState * instead of CPUARMState *. All internal functions have been renamed common_semi_ instead of arm_semi_ or arm_. Aside from the API change, there are no functional changes in this patch. Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210107170717.2098982-3-keithp@keithp.com> Message-Id: <20210108224256.2321-14-alex.bennee@linaro.org>
2021-01-18semihosting: Move ARM semihosting code to shared directoriesKeith Packard
This commit renames two files which provide ARM semihosting support so that they can be shared by other architectures: 1. target/arm/arm-semi.c -> hw/semihosting/common-semi.c 2. linux-user/arm/semihost.c -> linux-user/semihost.c The build system was modified use a new config variable, CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM softmmu and linux-user default configs. The contents of the source files has not been changed in this patch. Signed-off-by: Keith Packard <keithp@keithp.com> [AJB: rename arm-compat-semi, select SEMIHOSTING] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210107170717.2098982-2-keithp@keithp.com> Message-Id: <20210108224256.2321-13-alex.bennee@linaro.org>
2021-01-18target/arm: use official org.gnu.gdb.aarch64.sve layout for registersAlex Bennée
While GDB can work with any XML description given to it there is special handling for SVE registers on the GDB side which makes the users life a little better. The changes aren't that major and all the registers save the $vg reported the same. All that changes is: - report org.gnu.gdb.aarch64.sve - use gdb nomenclature for names and types - minor re-ordering of the types to match reference - re-enable ieee_half (as we know gdb supports it now) - $vg is now a 64 bit int - check $vN and $zN aliasing in test Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Luis Machado <luis.machado@linaro.org> Message-Id: <20210108224256.2321-11-alex.bennee@linaro.org>
2021-01-18gdbstub: drop CPUEnv from gdb_exit()Alex Bennée
gdb_exit() has never needed anything from env and I doubt we are going to start now. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210108224256.2321-8-alex.bennee@linaro.org>