aboutsummaryrefslogtreecommitdiff
path: root/target
AgeCommit message (Expand)Author
2018-10-02i386: Compile CPUX86State xsave_buf only when support KVM or HVFLiran Alon
2018-10-02target/i386: rename HF_SVMI_MASK to HF_GUEST_MASKPaolo Bonzini
2018-10-02target/i386: unify masking of interruptsPaolo Bonzini
2018-10-02target/i386: move x86_64_hregs to DisasContextEmilio G. Cota
2018-10-02target/i386: move cpu_tmp1_i64 to DisasContextEmilio G. Cota
2018-10-02target/i386: move cpu_tmp3_i32 to DisasContextEmilio G. Cota
2018-10-02target/i386: move cpu_tmp2_i32 to DisasContextEmilio G. Cota
2018-10-02target/i386: move cpu_ptr1 to DisasContextEmilio G. Cota
2018-10-02target/i386: move cpu_ptr0 to DisasContextEmilio G. Cota
2018-10-02target/i386: move cpu_tmp4 to DisasContextEmilio G. Cota
2018-10-02target/i386: move cpu_tmp0 to DisasContextEmilio G. Cota
2018-10-02target/i386: move cpu_T1 to DisasContextEmilio G. Cota
2018-10-02target/i386: move cpu_T0 to DisasContextEmilio G. Cota
2018-10-02target/i386: move cpu_A0 to DisasContextEmilio G. Cota
2018-10-02target/i386: move cpu_cc_srcT to DisasContextEmilio G. Cota
2018-10-02kvm: x86: Fix kvm_arch_fixup_msi_route for remap-less caseJan Kiszka
2018-10-01target/xtensa: extract gen_check_interrupts callMax Filippov
2018-10-01target/xtensa: make rsr/wsr helpers return voidMax Filippov
2018-10-01target/xtensa: extract unconditional TB termination via slot 0Max Filippov
2018-10-01target/xtensa: always end TB on CCOUNT access/CCOMPARE writeMax Filippov
2018-10-01target/xtensa: change SR number checks to assertionsMax Filippov
2018-10-01target/xtensa: extract unconditional TB terminationMax Filippov
2018-10-01target/xtensa: extract test for division by zeroMax Filippov
2018-10-01target/xtensa: extract test for cpdisabled exceptionMax Filippov
2018-10-01target/xtensa: extract test for alloca exceptionMax Filippov
2018-10-01target/xtensa: extract test for window underflow exceptionMax Filippov
2018-10-01target/xtensa: extract test for window overflow exceptionMax Filippov
2018-10-01target/xtensa: extract test for debug exceptionMax Filippov
2018-10-01target/xtensa: extract test for syscall instructionMax Filippov
2018-10-01target/xtensa: extract test for privileged instructionMax Filippov
2018-10-01target/xtensa: extract test for an illegal instructionMax Filippov
2018-09-25target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp modePeter Maydell
2018-09-25target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUsRichard Henderson
2018-09-25Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.1-20180925' into...Peter Maydell
2018-09-25Merge remote-tracking branch 'remotes/xtensa/tags/20180918-xtensa' into stagingPeter Maydell
2018-09-25target/ppc/cpu-models: Re-group the 970 CPUs together againThomas Huth
2018-09-24Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.1-20180907' into...Peter Maydell
2018-09-24Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-pullreq-201809...Peter Maydell
2018-09-17target/xtensa: support input from chardev consoleMax Filippov
2018-09-17target/xtensa: fix s32c1i TCGMemOp flagsMax Filippov
2018-09-17target/xtensa: fix FPU2000 bugsMax Filippov
2018-09-17target/xtensa: convert to do_transaction_failedMax Filippov
2018-09-05riscv: remove define cpu_init()Igor Mammedov
2018-09-05target/riscv: call gen_goto_tb on DISAS_TOO_MANYEmilio G. Cota
2018-09-05target/riscv: optimize indirect branchesEmilio G. Cota
2018-09-05target/riscv: optimize cross-page direct jumps in softmmuEmilio G. Cota
2018-09-05target/ppc/kvm: set vcpu as online/offlineNikunj A Dadhania
2018-09-04RISC-V: Simplify riscv_cpu_local_irqs_pendingMichael Clark
2018-09-04RISC-V: Improve page table walker spec complianceMichael Clark
2018-09-04RISC-V: Update address bits to support sv39 and sv48Michael Clark