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AgeCommit message (Expand)Author
2022-01-04ppc/ppc405: Restore TCR and STR write handlersCédric Le Goater
2022-01-04ppc/ppc405: Activate MMU logsCédric Le Goater
2022-01-04target/ppc: Print out literal exception names in logsCédric Le Goater
2022-01-04target/ppc: Remove static inlineCédric Le Goater
2022-01-04target/ppc: Check effective address validityCédric Le Goater
2022-01-04target/ppc: Improve logging in Radix MMUCédric Le Goater
2021-12-30target/hppa: Fix atomic_store_3 for STBYRichard Henderson
2021-12-23target/hppa: Fix deposit assert from trans_shrpw_immRichard Henderson
2021-12-20target/riscv: Enable bitmanip Zb[abcs] instructionsVineet Gupta
2021-12-20target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: update opivv_vadc_check() commentFrank Chang
2021-12-20target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...Frank Chang
2021-12-20target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang
2021-12-20target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()Frank Chang
2021-12-20target/riscv: rvv-1.0: add vsetivli instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11Frank Chang
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal estimate instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...Frank Chang
2021-12-20target/riscv: gdb: support vector registers for rv64 & rv32Hsiangkai Wang
2021-12-20target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not validFrank Chang
2021-12-20target/riscv: rvv-1.0: implement vstart CSRFrank Chang
2021-12-20target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bitsFrank Chang
2021-12-20target/riscv: rvv-1.0: narrowing floating-point/integer type-convertFrank Chang
2021-12-20target/riscv: add "set round to odd" rounding mode helper functionFrank Chang
2021-12-20target/riscv: rvv-1.0: widening floating-point/integer type-convertFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point/integer type-convert instructionsFrank Chang
2021-12-20target/riscv: introduce floating-point rounding mode enumFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point min/max instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: remove integer extract instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: remove vmford.vv and vmford.vfFrank Chang
2021-12-20target/riscv: rvv-1.0: remove widening saturating scaled multiply-addFrank Chang
2021-12-20target/riscv: rvv-1.0: single-width scaling shift instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: widening floating-point reduction instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: single-width floating-point reductionFrank Chang
2021-12-20target/riscv: rvv-1.0: narrowing fixed-point clip instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point slide instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: slide instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: mask-register logical instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point compare instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: integer comparison instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: single-width saturating add and subtract instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: widening integer multiply-add instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: narrowing integer right shift instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrowFrank Chang
2021-12-20target/riscv: rvv-1.0: single-width bit shift instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: single-width averaging add and subtract instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: integer extension instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: whole register move instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point scalar move instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point move instructionFrank Chang
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