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2017-09-15Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.11-20170915' ↵Peter Maydell
into staging ppc patch queue 2017-09-15 Here's the current batch of accumulated ppc patches. These are all pretty simple bugfixes or cleanups, no big new features here. # gpg: Signature made Fri 15 Sep 2017 04:50:00 BST # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.11-20170915: ppc/kvm: use kvm_vm_check_extension() in kvmppc_is_pr() spapr_events: use QTAILQ_FOREACH_SAFE() in spapr_clear_pending_events() spapr_cpu_core: cleaning up qdev_get_machine() calls spapr_pci: don't create 64-bit MMIO window if we don't need to spapr_pci: convert sprintf() to g_strdup_printf() spapr_cpu_core: fail gracefully with non-pseries machine types xics: fix several error leaks vfio, spapr: Fix levels calculation spapr_pci: handle FDT creation errors with _FDT() spapr_pci: use the common _FDT() helper spapr: fix CAS-generated reset ppc/xive: fix OV5_XIVE_EXPLOIT bits spapr: only update SDR1 once per-cpu during CAS spapr_pci: use g_strdup_printf() spapr_pci: drop useless check in spapr_populate_pci_child_dt() spapr_pci: drop useless check in spapr_phb_vfio_get_loc_code() hw/ppc/spapr.c: cleaning up qdev_get_machine() calls net: Add SunGEM device emulation as found on Apple UniNorth Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-15ppc/kvm: use kvm_vm_check_extension() in kvmppc_is_pr()Greg Kurz
If the host has both KVM PR and KVM HV loaded and we pass: -machine pseries,accel=kvm,kvm-type=PR the kvmppc_is_pr() returns false instead of true. Since the helper is mostly used as fallback, it doesn't have any real impact with recent kernels. A notable exception is the workaround to allow migration between compatible hosts with different PVRs (eg, POWER8 and POWER8E), since KVM still doesn't provide a way to check if a specific PVR is supported (see commit c363a37a450f for details). According to the official KVM API documentation [1], KVM_PPC_GET_PVINFO is "vm ioctl", but we check it as a global ioctl. The following function in KVM is hence called with kvm == NULL and considers we're in HV mode. int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) { int r; /* Assume we're using HV mode when the HV module is loaded */ int hv_enabled = kvmppc_hv_ops ? 1 : 0; if (kvm) { /* * Hooray - we know which VM type we're running on. Depend on * that rather than the guess above. */ hv_enabled = is_kvmppc_hv_enabled(kvm); } Let's use kvm_vm_check_extension() to fix the issue. [1] https://www.kernel.org/doc/Documentation/virtual/kvm/api.txt Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-14target/arm: Avoid an extra temporary for store_exclusiveRichard Henderson
Instead of copying addr to a local temp, reuse the value (which we have just compared as equal) already saved in cpu_exclusive_addr. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 20170908163859.29820-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-14AArch64: Fix single stepping of ERET instructionJaroslaw Pelczar
Previously when single stepping through ERET instruction via GDB would result in debugger entering the "next" PC after ERET instruction. When debugging in kernel mode, this will also cause unintended behavior, because debugger will try to access memory from EL0 point of view. Signed-off-by: Jaroslaw Pelczar <j.pelczar@samsung.com> Message-id: 001c01d32895$483027f0$d89077d0$@samsung.com Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-14target/arm: Rename 'type' to 'excret' in do_v7m_exception_exit()Peter Maydell
In the v7M and v8M ARM ARM, the magic exception return values are referred to as EXC_RETURN values, and in QEMU we use V7M_EXCRET_* constants to define bits within them. Rename the 'type' variable which holds the exception return value in do_v7m_exception_exit() to excret, making it clearer that it does hold an EXC_RETURN value. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1505137930-13255-8-git-send-email-peter.maydell@linaro.org
2017-09-14target/arm: Add and use defines for EXCRET constantsPeter Maydell
The exception-return magic values get some new bits in v8M, which makes some bit definitions for them worthwhile. We don't use the bit definitions for the switch on the low bits which checks the return type for v7M, because this is defined in the v7M ARM ARM as a set of valid values rather than via per-bit checks. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1505137930-13255-7-git-send-email-peter.maydell@linaro.org
2017-09-14target/arm: Remove unnecessary '| 0xf0000000' from do_v7m_exception_exit()Peter Maydell
In do_v7m_exception_exit(), there's no need to force the high 4 bits of 'type' to 1 when calling v7m_exception_taken(), because we know that they're always 1 or we could not have got to this "handle return to magic exception return address" code. Remove the unnecessary ORs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1505137930-13255-6-git-send-email-peter.maydell@linaro.org
2017-09-14target/arm: Get PRECISERR and IBUSERR the right way roundPeter Maydell
For a bus fault, the M profile BFSR bit PRECISERR means a bus fault on a data access, and IBUSERR means a bus fault on an instruction access. We had these the wrong way around; fix this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1505137930-13255-4-git-send-email-peter.maydell@linaro.org
2017-09-14target/arm: Clear exclusive monitor on v7M reset, exception entry/exitPeter Maydell
For M profile we must clear the exclusive monitor on reset, exception entry and exception exit. We weren't doing any of these things; fix this bug. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1505137930-13255-3-git-send-email-peter.maydell@linaro.org
2017-09-14target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2Peter Maydell
Use a symbolic constant M_REG_NUM_BANKS for the array size for registers which are banked by M profile security state, rather than hardcoding lots of 2s. Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1505137930-13255-2-git-send-email-peter.maydell@linaro.org
2017-09-14hmp: fix "dump-quest-memory" segfault (arm)Laurent Vivier
Running QEMU with qemu-system-aarch64 -M none -nographic -m 256 and executing dump-guest-memory /dev/null 0 8192 results in segfault Fix by checking if we have CPU, and exit with error if there is no CPU: (qemu) dump-guest-memory /dev/null this feature or command is not currently supported Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <20170913142036.2469-3-lvivier@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2017-09-14hmp: fix "dump-quest-memory" segfault (ppc)Laurent Vivier
Running QEMU with qemu-system-ppc64 -M none -nographic -m 256 and executing dump-guest-memory /dev/null 0 8192 results in segfault Fix by checking if we have CPU, and exit with error if there is no CPU: (qemu) dump-guest-memory /dev/null this feature or command is not currently supported Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20170913142036.2469-2-lvivier@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2017-09-14sparc: Fix typedef clashDr. David Alan Gilbert
Older compilers (rhel6) don't like redefinition of typedefs Fixes: 12a6c15ef31c98ecefa63e91ac36955383038384 Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170914123609.497-1-dgilbert@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-10target/m68k: Switch fpu_rom from make_floatx80() to make_floatx80_init()Kamil Rytarowski
GCC 4.7.2 on SunOS reports that the values assigned to array members are not real constants: target/m68k/fpu_helper.c:32:5: error: initializer element is not constant target/m68k/fpu_helper.c:32:5: error: (near initialization for 'fpu_rom[0]') rules.mak:66: recipe for target 'target/m68k/fpu_helper.o' failed Convert the array to make_floatx80_init() to fix it. Replace floatx80_pi-like constants with make_floatx80_init() as they are defined as make_floatx80(). This fixes build on SmartOS (Joyent). Signed-off-by: Kamil Rytarowski <n54@gmx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170904212306.3020-1-n54@gmx.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-09-08Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.11-20170908' ↵Peter Maydell
into staging ppc patch queue 2017-09-08 This is the first batch of ppc related patches for qemu-2.11, and it's accumulated quite a few things. Includes: * A cleanup to handling of ppc cpu models from Igor * First parts of fixes to handling of guest vs. host SMT modes from Sam Bobroff * Preliminary patches towards supporting the Sam460 board from Balaton Zoltan * Several fixes for hotplug logic * Assorted other fixes and cleanups # gpg: Signature made Fri 08 Sep 2017 06:28:42 BST # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.11-20170908: (40 commits) ppc: spapr: Move VCPU ID calculation into sPAPR ppc: remove non implemented cpu models ppc: drop caching ObjectClass from PowerPCCPUAlias ppc: simplify cpu model lookup by PVR ppc: replace inter-function cyclic dependency/recurssion with 2 simple lookups ppc: make cpu alias point only to real cpu models ppc: make cpu_model translation to type consistent ppc: use macros to make cpu type name from string literal target/ppc: Remove old STATUS file PPC: KVM: Support machine option to set VSMT mode spapr: fallback to raw mode if best compat mode cannot be set during CAS hw/nvram/spapr_nvram: Device can not be created by the users hw/ppc/spapr_cpu_core: Add a proper check for spapr machine ppc4xx: Export ECB and PLB emulation ppc4xx_i2c: Move to hw/i2c ppc4xx_i2c: QOMify ppc4xx: Split off 4xx I2C emulation from ppc405_uc to its own file ppc4xx: Make MAL emulation more generic ppc4xx: Move MAL from ppc405_uc to ppc4xx_devs spapr_iommu: Realloc guest visible TCE table when hot(un)plugging vfio-pci ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-08Merge remote-tracking branch 'remotes/rth/tags/pull-pa-20170907' into stagingPeter Maydell
Conversion to TranslatorOps # gpg: Signature made Thu 07 Sep 2017 19:42:48 BST # gpg: using RSA key 0x64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-pa-20170907: target/hppa: Convert to TranslatorOps target/hppa: Convert to DisasContextBase target/hppa: Convert to DisasJumpType Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-08ppc: spapr: Move VCPU ID calculation into sPAPRSam Bobroff
Move the calculation of a CPU's VCPU ID out of the generic PPC code (ppc_cpu_realizefn()) and into sPAPR specific code (spapr_cpu_core_realize()) where it belongs. Unfortunately, due to the way things are ordered, we still need to default the VCPU ID in ppc_cpu_realizfn() but at least doing that doesn't require any interaction with sPAPR. Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc: remove non implemented cpu modelsIgor Mammedov
Remove cpu models that aren't implemented and are not compiled/tested since they are under TODO ifdef which isn't defined in sources. If someone really needs a removed model he/she should add as regular one with corresponding implementation. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc: drop caching ObjectClass from PowerPCCPUAliasIgor Mammedov
Caching there practically doesn't give any benefits and that at slow path druring querying supported CPU list. But it introduces non conventional path of where from comes used CPU type name (kvm_ppc_register_host_cpu_type). Taking in account that kvm_ppc_register_host_cpu_type() fixes up models the aliases point to, it's sufficient to make ppc_cpu_class_by_name() translate cpu alias to correct cpu type name. So drop PowerPCCPUAlias::oc field + ppc_cpu_class_by_alias() and let ppc_cpu_class_by_name() do conversion to cpu type name, which simplifies code a little bit saving ~20LOC and trouble wondering why ppc_cpu_class_by_alias() is necessary. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc: simplify cpu model lookup by PVRIgor Mammedov
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc: replace inter-function cyclic dependency/recurssion with 2 simple lookupsIgor Mammedov
previous patches cleaned up cpu model/alias naming which allows to simplify cpu model/alias to cpu type lookup a bit byt removing recurssion and dependency of ppc_cpu_class_by_name() / ppc_cpu_class_by_alias() on each other. Besides of simplifying code it reduces it by ~15LOC. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc: make cpu alias point only to real cpu modelsIgor Mammedov
alias pointing to another alias forces lookup code to do recurrsive translation till real cpu model is reached. Drop this nonsence and make each alias point to cpu model that has corresponding CPU type. It will allow to drop recurrsion in cpu model translation code and actually make ppc_cpu_aliases[] content use PowerPCCPUAlias fields properly (i.e. alias goes into .alias and model goes into .model) While at it add TODO defines around aliases that point to cpu models excluded by the same TODO defines. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc: make cpu_model translation to type consistentIgor Mammedov
PPC handles -cpu FOO rather incosistently, i.e. it does case-insensitive matching of FOO to a CPU type (see: ppc_cpu_compare_class_name) but handles alias names as case-sensitive, as result: # qemu-system-ppc64 -M mac99 -cpu g3 qemu-system-ppc64: unable to find CPU model ' kN�U' # qemu-system-ppc64 -cpu 970MP_V1.1 qemu-system-ppc64: Unable to find sPAPR CPU Core definition while # qemu-system-ppc64 -M mac99 -cpu G3 # qemu-system-ppc64 -cpu 970MP_v1.1 start up just fine. Considering we can't take case-insensitive matching away, make it case-insensitive for all alias/type/core_type lookups. As side effect it allows to remove duplicate core types which are the same except of using different cased letters in name. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc: use macros to make cpu type name from string literalIgor Mammedov
Replace "-" TYPE_POWERPC_CPU when composing cpu type name from cpu model string literal and the same pattern in format strings with POWERPC_CPU_TYPE_SUFFIX and POWERPC_CPU_TYPE_NAME(model) macroses like we do in x86. Later POWERPC_CPU_TYPE_NAME() will be used to define default cpu type per machine type and as bonus it will be consistent and easy grep-able pattern across all other targets that I'm plannig to treat the same way. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08target/ppc: Remove old STATUS fileThomas Huth
The target/ppc/STATUS file has seen its last real update 10 years ago - so the information in there is not up to date anymore. Since nobody seems to care about this file, let's simply remove it. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08PPC: KVM: Support machine option to set VSMT modeSam Bobroff
KVM now allows writing to KVM_CAP_PPC_SMT which has previously been read only. Doing so causes KVM to act, for that VM, as if the host's SMT mode was the given value. This is particularly important on Power 9 systems because their default value is 1, but they are able to support values up to 8. This patch introduces a way to control this capability via a new machine property called VSMT ("Virtual SMT"). If the value is not set on the command line a default is chosen that is, when possible, compatible with legacy systems. Note that the intialization of KVM_CAP_PPC_SMT has changed slightly because it has changed (in KVM) from a global capability to a VM-specific one. This won't cause a problem on older KVMs because VM capabilities fall back to global ones. Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc64: introduce e6500KONRAD Frederic
This introduces e6500 core. Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08booke206: allow to specify an mmucfg value at the initKONRAD Frederic
This allows to init the MMUCFG SPR with a non NULL value. Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08booke206: fix tlbnps for fixed size TLBKONRAD Frederic
Some OS don't populate the TSIZE field when using a fixed size TLB which result in a 1KB TLB. When the TLB is a fixed size TLB the TSIZE field should be ignored. Fix this wrong behavior with MAV 2.0. Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08booke206: fix booke206_tlbnps for mav 2.0KONRAD Frederic
This fixes booke206_tlbnps for MAV 2.0 by checking the MMUCFG register and return directly the right tlbnps instead of computing it from non existing field. Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc: spapr: Make VCPU ID handling private to SPAPRSam Bobroff
The concept of a VCPU ID that differs from the CPU's index (cpu->cpu_index) exists only within SPAPR machines so, move the functions ppc_get_vcpu_id() and ppc_get_cpu_by_vcpu_id() into spapr.c and rename them appropriately. Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc: spapr: Rename cpu_dt_id to vcpu_idSam Bobroff
This field actually records the VCPU ID used by KVM and, although the value is also used in the device tree it is primarily the VCPU ID so rename it as such. Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> [dwg: Updated comment missed in cpu.h] Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-07target/hppa: Convert to TranslatorOpsRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07target/hppa: Convert to DisasContextBaseRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07target/hppa: Convert to DisasJumpTypeRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07target/alpha: Switch to do_transaction_failed() hookPeter Maydell
Switch the alpha target from the old unassigned_access hook to the new do_transaction_failed hook. This allows us to resolve a ??? in the old hook implementation. The only part of the alpha target that does physical memory accesses is reading the page table -- add a TODO comment there to the effect that we should handle bus faults on page table walks. (Since the palcode doesn't actually do anything useful on a bus fault anyway it's a bit moot for now.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <1502196172-13818-1-git-send-email-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-09-07target/alpha: Convert to TranslatorOpsRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07target/alpha: Convert to DisasContextBaseRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07target/alpha: Convert to DisasJumpTypeRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20170907' into staging target-arm: * cleanups converting to DEFINE_PROP_LINK * allwinner-a10: mark as not user-creatable * initial patches working towards ARMv8M support * implement generating aborts on memory transaction failures * make BXJ behave correctly (ie not UNDEF) on ARMv6-and-later # gpg: Signature made Thu 07 Sep 2017 14:26:07 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20170907: (31 commits) target/arm: Add Jazelle feature target/arm: Implement new do_transaction_failed hook hw/arm: Set ignore_memory_transaction_failures for most ARM boards boards.h: Define new flag ignore_memory_transaction_failures target/arm: Implement BXNS, and banked stack pointers target/arm: Move regime_is_secure() to target/arm/internals.h target/arm: Make CFSR register banked for v8M target/arm: Make MMFAR banked for v8M target/arm: Make CCR register banked for v8M target/arm: Make MPU_CTRL register banked for v8M target/arm: Make MPU_RNR register banked for v8M target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M target/arm: Make VTOR register banked for v8M nvic: Add NS alias SCS region target/arm: Make CONTROL register banked for v8M target/arm: Make FAULTMASK register banked for v8M target/arm: Make PRIMASK register banked for v8M target/arm: Make BASEPRI register banked for v8M target/arm: Add MMU indexes for secure v8M ... # Conflicts: # target/arm/translate.c
2017-09-07target/arm: Add Jazelle featurePortia Stephens
This adds a feature bit indicating support of the (trivial) Jazelle implementation if ARM_FEATURE_V6 is set or if the processor is arm926 or arm1026. This fixes the issue that any BXJ instruction will result in an illegal_op. BXJ instructions will now check if the architecture supports ARM_FEATURE_JAZELLE. Signed-off-by: Portia Stephens <portia.stephens@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 20170905211232.11092-1-portia.stephens@xilinx.com [PMM: edited commit message and comment text a bit] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-07target/arm: Implement new do_transaction_failed hookPeter Maydell
Implement the new do_transaction_failed hook for ARM, which should cause the CPU to take a prefetch abort or data abort. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1504626814-23124-4-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Implement BXNS, and banked stack pointersPeter Maydell
Implement the BXNS v8M instruction, which is like BX but will do a jump-and-switch-to-NonSecure if the branch target address has bit 0 clear. This is the first piece of code which implements "switch to the other security state", so the commit also includes the code to switch the stack pointers around, which is the only complicated part of switching security state. BLXNS is more complicated than just "BXNS but set the link register", so we leave it for a separate commit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-21-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Move regime_is_secure() to target/arm/internals.hPeter Maydell
Move the regime_is_secure() utility function to internals.h; we are going to want to call it from translate.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-20-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make CFSR register banked for v8MPeter Maydell
Make the CFSR register banked if v8M security extensions are enabled. Not all the bits in this register are banked: the BFSR bits [15:8] are shared between S and NS, and we store them in the NS copy of the register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-19-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make MMFAR banked for v8MPeter Maydell
Make the MMFAR register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-18-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make CCR register banked for v8MPeter Maydell
Make the CCR register banked if v8M security extensions are enabled. This is slightly more complicated than the other "add banking" patches because there is one bit in the register which is not banked. We keep the live data in the NS copy of the register, and adjust it on register reads and writes. (Since we don't currently implement the behaviour that the bit controls, there is nowhere else that needs to care.) This patch includes the enforcement of the bits which are newly RES1 in ARMv8M. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1503414539-28762-17-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make MPU_CTRL register banked for v8MPeter Maydell
Make the MPU_CTRL register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-16-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make MPU_RNR register banked for v8MPeter Maydell
Make the MPU_RNR register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-15-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make MPU_RBAR, MPU_RLAR banked for v8MPeter Maydell
Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security extensions are enabled. We can freely add more items to vmstate_m_security without breaking migration compatibility, because no CPU currently has the ARM_FEATURE_M_SECURITY bit enabled and so this subsection is not yet used by anything. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-14-git-send-email-peter.maydell@linaro.org
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