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AgeCommit message (Expand)Author
2021-11-03Hexagon HVX (target/hexagon) helper overrides - vector max/minTaylor Simpson
2021-11-03Hexagon HVX (target/hexagon) helper overrides - vector shiftsTaylor Simpson
2021-11-03Hexagon HVX (target/hexagon) helper overrides - vector add & subTaylor Simpson
2021-11-03Hexagon HVX (target/hexagon) helper overrides - vector assign & cmovTaylor Simpson
2021-11-03Hexagon HVX (target/hexagon) helper overrides for histogram instructionsTaylor Simpson
2021-11-03Hexagon HVX (target/hexagon) helper overrides infrastructureTaylor Simpson
2021-11-03Hexagon HVX (target/hexagon) TCG generationTaylor Simpson
2021-11-03Hexagon HVX (target/hexagon) helper functionsTaylor Simpson
2021-11-03Hexagon HVX (target/hexagon) instruction utility functionsTaylor Simpson
2021-11-03Hexagon HVX (target/hexagon) C preprocessor for decode treeTaylor Simpson
2021-11-03Hexagon HVX (target/hexagon) semantics generator - part 2Taylor Simpson
2021-11-03Hexagon HVX (target/hexagon) semantics generatorTaylor Simpson
2021-11-03Hexagon HVX (target/hexagon) import macro definitionsTaylor Simpson
2021-11-03Hexagon HVX (target/hexagon) macrosTaylor Simpson
2021-11-03Hexagon HVX (target/hexagon) instruction attributesTaylor Simpson
2021-11-03Hexagon HVX (target/hexagon) register namesTaylor Simpson
2021-11-03Hexagon HVX (target/hexagon) add Hexagon Vector eXtensions (HVX) to coreTaylor Simpson
2021-11-03Hexagon HVX (target/hexagon) READMETaylor Simpson
2021-10-29Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' in...Richard Henderson
2021-10-29target/i386: Remove core-capability in Snowridge CPU modelChenyi Qiang
2021-10-29Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-202...Richard Henderson
2021-10-29Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211028' into stagingRichard Henderson
2021-10-29target/riscv: change the api for RVF/RVD fmin/fmaxChih-Min Chao
2021-10-29target/riscv: remove force HS exceptionJose Martins
2021-10-29target/riscv: fix VS interrupts forwarding to HSJose Martins
2021-10-28Hexagon (target/hexagon) put writes to USR into temp until commitTaylor Simpson
2021-10-28Hexagon (target/hexagon) more tcg_constant_*Taylor Simpson
2021-10-28target/riscv: Allow experimental J-ext to be turned onAlexey Baturo
2021-10-28target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev
2021-10-28target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...Alexey Baturo
2021-10-28target/riscv: Print new PM CSRs in QEMU logsAlexey Baturo
2021-10-28target/riscv: Add J extension state descriptionAlexey Baturo
2021-10-28target/riscv: Support CSRs required for RISC-V PM extension except for the h-...Alexey Baturo
2021-10-28target/riscv: Add CSR defines for RISC-V PM extensionAlexey Baturo
2021-10-28target/riscv: Add J-extension into RISC-VAlexey Baturo
2021-10-27host-utils: add 128-bit quotient support to divu128/divs128Luis Pires
2021-10-27host-utils: move checks out of divu128/divs128Luis Pires
2021-10-23Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.2-pull...Richard Henderson
2021-10-22disas/nios2: Simplify endianess conversionPhilippe Mathieu-Daudé
2021-10-22target/riscv: Compute mstatus.sd on demandRichard Henderson
2021-10-22target/riscv: Use riscv_csrrw_debug for cpu_dumpRichard Henderson
2021-10-22target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson
2021-10-22target/riscv: Use gen_unary_per_ol for RVBRichard Henderson
2021-10-22target/riscv: Adjust trans_rev8_32 for riscv64Richard Henderson
2021-10-22target/riscv: Use gen_arith_per_ol for RVMRichard Henderson
2021-10-22target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson
2021-10-22target/riscv: Replace is_32bit with get_xl/get_xlenRichard Henderson
2021-10-22target/riscv: Properly check SEW in amo_opRichard Henderson
2021-10-22target/riscv: Use REQUIRE_64BIT in amo_check64Richard Henderson
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson