Age | Commit message (Expand) | Author |
2021-11-03 | Hexagon HVX (target/hexagon) helper overrides - vector max/min | Taylor Simpson |
2021-11-03 | Hexagon HVX (target/hexagon) helper overrides - vector shifts | Taylor Simpson |
2021-11-03 | Hexagon HVX (target/hexagon) helper overrides - vector add & sub | Taylor Simpson |
2021-11-03 | Hexagon HVX (target/hexagon) helper overrides - vector assign & cmov | Taylor Simpson |
2021-11-03 | Hexagon HVX (target/hexagon) helper overrides for histogram instructions | Taylor Simpson |
2021-11-03 | Hexagon HVX (target/hexagon) helper overrides infrastructure | Taylor Simpson |
2021-11-03 | Hexagon HVX (target/hexagon) TCG generation | Taylor Simpson |
2021-11-03 | Hexagon HVX (target/hexagon) helper functions | Taylor Simpson |
2021-11-03 | Hexagon HVX (target/hexagon) instruction utility functions | Taylor Simpson |
2021-11-03 | Hexagon HVX (target/hexagon) C preprocessor for decode tree | Taylor Simpson |
2021-11-03 | Hexagon HVX (target/hexagon) semantics generator - part 2 | Taylor Simpson |
2021-11-03 | Hexagon HVX (target/hexagon) semantics generator | Taylor Simpson |
2021-11-03 | Hexagon HVX (target/hexagon) import macro definitions | Taylor Simpson |
2021-11-03 | Hexagon HVX (target/hexagon) macros | Taylor Simpson |
2021-11-03 | Hexagon HVX (target/hexagon) instruction attributes | Taylor Simpson |
2021-11-03 | Hexagon HVX (target/hexagon) register names | Taylor Simpson |
2021-11-03 | Hexagon HVX (target/hexagon) add Hexagon Vector eXtensions (HVX) to core | Taylor Simpson |
2021-11-03 | Hexagon HVX (target/hexagon) README | Taylor Simpson |
2021-10-29 | Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' in... | Richard Henderson |
2021-10-29 | target/i386: Remove core-capability in Snowridge CPU model | Chenyi Qiang |
2021-10-29 | Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-202... | Richard Henderson |
2021-10-29 | Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211028' into staging | Richard Henderson |
2021-10-29 | target/riscv: change the api for RVF/RVD fmin/fmax | Chih-Min Chao |
2021-10-29 | target/riscv: remove force HS exception | Jose Martins |
2021-10-29 | target/riscv: fix VS interrupts forwarding to HS | Jose Martins |
2021-10-28 | Hexagon (target/hexagon) put writes to USR into temp until commit | Taylor Simpson |
2021-10-28 | Hexagon (target/hexagon) more tcg_constant_* | Taylor Simpson |
2021-10-28 | target/riscv: Allow experimental J-ext to be turned on | Alexey Baturo |
2021-10-28 | target/riscv: Implement address masking functions required for RISC-V Pointer... | Anatoly Parshintsev |
2021-10-28 | target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr... | Alexey Baturo |
2021-10-28 | target/riscv: Print new PM CSRs in QEMU logs | Alexey Baturo |
2021-10-28 | target/riscv: Add J extension state description | Alexey Baturo |
2021-10-28 | target/riscv: Support CSRs required for RISC-V PM extension except for the h-... | Alexey Baturo |
2021-10-28 | target/riscv: Add CSR defines for RISC-V PM extension | Alexey Baturo |
2021-10-28 | target/riscv: Add J-extension into RISC-V | Alexey Baturo |
2021-10-27 | host-utils: add 128-bit quotient support to divu128/divs128 | Luis Pires |
2021-10-27 | host-utils: move checks out of divu128/divs128 | Luis Pires |
2021-10-23 | Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.2-pull... | Richard Henderson |
2021-10-22 | disas/nios2: Simplify endianess conversion | Philippe Mathieu-Daudé |
2021-10-22 | target/riscv: Compute mstatus.sd on demand | Richard Henderson |
2021-10-22 | target/riscv: Use riscv_csrrw_debug for cpu_dump | Richard Henderson |
2021-10-22 | target/riscv: Use gen_shift*_per_ol for RVB, RVI | Richard Henderson |
2021-10-22 | target/riscv: Use gen_unary_per_ol for RVB | Richard Henderson |
2021-10-22 | target/riscv: Adjust trans_rev8_32 for riscv64 | Richard Henderson |
2021-10-22 | target/riscv: Use gen_arith_per_ol for RVM | Richard Henderson |
2021-10-22 | target/riscv: Replace DisasContext.w with DisasContext.ol | Richard Henderson |
2021-10-22 | target/riscv: Replace is_32bit with get_xl/get_xlen | Richard Henderson |
2021-10-22 | target/riscv: Properly check SEW in amo_op | Richard Henderson |
2021-10-22 | target/riscv: Use REQUIRE_64BIT in amo_check64 | Richard Henderson |
2021-10-22 | target/riscv: Add MXL/SXL/UXL to TB_FLAGS | Richard Henderson |