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2023-02-27target/arm: Move hflags code into the tcg directoryFabiano Rosas
The hflags are used only for TCG code, so introduce a new file hflags.c to keep that code. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-27target/arm: Wrap arm_rebuild_hflags calls with tcg_enabledFabiano Rosas
This is in preparation to moving the hflags code into its own file under the tcg/ directory. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-27target/arm: Move psci.c into the tcg directoryClaudio Fontana
Signed-off-by: Claudio Fontana <cfontana@suse.de> Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-27target/arm: move helpers to tcg/Claudio Fontana
Signed-off-by: Claudio Fontana <cfontana@suse.de> Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-27target/arm: move translate modules to tcg/Fabiano Rosas
Introduce the target/arm/tcg directory. Its purpose is to hold the TCG code that is selected by CONFIG_TCG. Signed-off-by: Claudio Fontana <cfontana@suse.de> Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-27target/arm: Wrap TCG-only code in debug_helper.cFabiano Rosas
The next few patches will move helpers under CONFIG_TCG. We'd prefer to keep the debug helpers and debug registers close together, so rearrange the file a bit to be able to wrap the helpers with a TCG ifdef. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-27target/arm: Wrap breakpoint/watchpoint updates with tcg_enabledFabiano Rosas
This is in preparation for restricting compilation of some parts of debug_helper.c to TCG only. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-27Merge tag 'pull-request-2023-02-27' of https://gitlab.com/thuth/qemu into ↵Peter Maydell
staging * Simplify device casting in w/vfio/ccw.c * Fix memory corruption in the s390x dump code * Various s390x TCG clean-ups * s390x PV support for asynchronous teardown for reboot * qemu-keymap related fixes * Improvements for the duration of the gitlab-CI * Deprecate the "-no-acpi" command line switch # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmP8lVURHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbWYkg//RTKsG0+HGMtnKvjTA5NzLIJrWAQfSPfh # ABkxNHoscReae8LGquFfeTy9cN/uA051e/P06WfPXAkg3Uj72JKHHs/ncm5VhApY # 7moOCIHlvFRAsy5TKYoInM+Yo0jov7vgKqqJcS3AL3hwhmvEwPwKr0cpZLNfKV8p # GD+XM453g0AFn2jDFoXDsnHX3zco+7sd4dQN4olSrkd/gDel2UQ5JE4gJ/o6Qgys # GW4vb+NpxQ6W3mSlU+ClTr03ZljPkascBS7tZO8Fwn+J3Wv4UTNLlM1JFXQhC3v8 # x9HpVpk4HW6C/hiPcsMpZRlXBb/HklkAhDxZ6tjTnQLRvbJ/o2uISJt+ZgeH9zeQ # Ae4Ap7yPxsuGbx2twzbGoyEPAJj18hW7EUd6KromFqy877svmyRYs3NXQqSJOEmh # Pv7VriUe6esyyVSXWjA6g2imo5pIhWxxRlsNVrrp8vOJNYT+ygBIFqu28ngwk86H # jZOLqekEkQrNkwZZLuoxm8FyCAvzfMBeHQFlDnL4a3114dlC6X3/cJqCZ5htTaO+ # t7CL6QcepRh0NQPw1jRlUCARZK+WocjwwcmzgVzSKKzGpdg/EJC8Sg54l7wdVQCp # jY3HEUWHHHmrqe3IefrzadRQhsB9xKcNdUaZmetRUm+ohgSc9S0cfpVXNwT+G3+M # a47dp9ueI6Q= # =wDFZ # -----END PGP SIGNATURE----- # gpg: Signature made Mon 27 Feb 2023 11:34:45 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2023-02-27' of https://gitlab.com/thuth/qemu: (33 commits) Deprecate the "-no-acpi" command line switch gitlab-ci.d/base: Mark jobs as interruptible by default gitlab-ci.d: Build with --enable-fdt=system by default gitlab-ci.d/buildtest-template: Simplify the configure step gitlab-ci.d/buildtest: Disintegrate the build-coroutine-sigaltstack job gitlab-ci.d/buildtest: Remove aarch64-softmmu from the build-system-ubuntu job Updated the FSF address to <https://www.gnu.org/licenses/> meson: fix dependency on qemu-keymap qemu-keymap: Silence memory leak warning from Clang's sanitizer configure: Add 'mkdir build' check tests/tcg/s390x: Add sam.S tests/tcg/s390x: Add bal.S target/s390x: Use tcg_constant_* in translate_vx.c.inc target/s390x: Use tcg_constant_i32 for fpinst_extract_m34 target/s390x: Use tcg_constant_* for DisasCompare target/s390x: Use tcg_constant_* in local contexts s390x/pv: Add support for asynchronous teardown for reboot target/s390x: Hoist some computation in access_memmove target/s390x: Inline do_access_{get,set}_byte target/s390x: Remove TLB_NOTDIRTY workarounds ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-27target/i386: Fix BZHI instructionRichard Henderson
We did not correctly handle N >= operand size. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1374 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230114233206.3118472-1-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-02-27target/s390x: Use tcg_constant_* in translate_vx.c.incRichard Henderson
In most cases, this is a simple local allocate and free replaced by tcg_constant_*. In three cases, a variable temp was initialized with a constant value -- reorg to localize the constant. In gen_acc, this fixes a leak. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230220184052.163465-5-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-02-27target/s390x: Use tcg_constant_i32 for fpinst_extract_m34Richard Henderson
Return a constant or NULL, which means the free may be removed from all callers of fpinst_extract_m34. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230220184052.163465-4-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-02-27target/s390x: Use tcg_constant_* for DisasCompareRichard Henderson
The a and b fields are not modified by the consumer, and while we need not free a constant, tcg will quietly ignore such frees, so free_compare need not be changed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230220184052.163465-3-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-02-27target/s390x: Use tcg_constant_* in local contextsRichard Henderson
Replace tcg_const_* with tcg_constant_* in contexts where the free to remove is nearby. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20230220184052.163465-2-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-02-27target/s390x: Hoist some computation in access_memmoveRichard Henderson
Ensure that the total length is in a local variable across the byte loop. Compute size1 difference once. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20230109201856.3916639-8-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-02-27target/s390x: Inline do_access_{get,set}_byteRichard Henderson
Inline into the parent functions with a simple test to select the page, and a new define to remove ifdefs. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20230109201856.3916639-7-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-02-27target/s390x: Remove TLB_NOTDIRTY workaroundsRichard Henderson
When this code was written, it was using tlb_vaddr_to_host, which does not handle TLB_DIRTY. Since then, it has been converted to probe_access_flags, which does. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Hildenbrand <david@redhat.com> Message-Id: <20230109201856.3916639-6-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-02-27target/s390x: Tidy access_prepare_nfRichard Henderson
Assign to access struct immediately, rather than waiting until the end of the function. This means we can pass address of haddr struct members instead of allocating extra space on the local stack. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20230109201856.3916639-5-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-02-27target/s390x: Use void* for haddr in S390AccessRichard Henderson
The interface from probe_access_flags is void*, and matching that will be helpful. We already rely on the gcc extension for byte arithmetic on void*. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20230109201856.3916639-4-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-02-27target/s390x: Pass S390Access pointer into access_prepareRichard Henderson
Passing a pointer from the caller down to access_prepare_nf eliminates a structure copy. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20230109201856.3916639-3-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-02-27target/s390x: Fix s390_probe_access for user-onlyRichard Henderson
In db9aab5783a2 we broke the contract of s390_probe_access, in that it no longer returned an exception code, nor set __excp_addr. Fix both. Reported-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20230109201856.3916639-2-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-02-27target/s390x/arch_dump: Simplify memory allocation in s390x_write_elf64_notes()Thomas Huth
We are not on a hot path here, so there is no real need for the logic here with the split heap and stack space allocation. Simplify it by always allocating memory from the heap. Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230215085703.746788-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-02-27target/s390x/arch_dump: Fix memory corruption in s390x_write_elf64_notes()Thomas Huth
"note_size" can be smaller than sizeof(note), so unconditionally calling memset(notep, 0, sizeof(note)) could cause a memory corruption here in case notep has been allocated dynamically, thus let's use note_size as length argument for memset() instead. Reported-by: Sebastian Mitterle <smitterl@redhat.com> Fixes: 113d8f4e95 ("s390x: pv: Add dump support") Message-Id: <20230214141056.680969-1-thuth@redhat.com> Reviewed-by: Janosch Frank <frankja@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-02-26Merge tag 'pull-riscv-to-apply-20230224' of github.com:palmer-dabbelt/qemu ↵Peter Maydell
into staging Fourth RISC-V PR for QEMU 8.0, Attempt 2 * A triplet of cleanups to the kernel/initrd loader that avoids duplication between the various boards. * Weiwei Li, Daniel Henrique Barboza, and Liu Zhiwei have been added as reviewers. Thanks for the help! * A fix for PMP matching to avoid incorrectly appling the default permissions on PMP permission violations. * A cleanup to avoid an unnecessary avoid env_archcpu() in cpu_get_tb_cpu_state(). * Fixes for the vector slide instructions to avoid truncating 64-bit values (such as doubles) on 32-bit targets. # -----BEGIN PGP SIGNATURE----- # # iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmP5Br8THHBhbG1lckBk # YWJiZWx0LmNvbQAKCRAuExnzX7sYiT4RD/9hdSlQlR1g/2h4fbCJ3U0GvyNH0T7N # mt3AX8hFvmfR1O63qqVVebJSHM1dTm6WsA19vKE5tdtbjV5V8UZuBTSqYeRBSrLd # LK9IHhwv3k9OQ/EG8CgRo7HEMxAurpC26zTf3chnfwa1Wyl5XxCXNx5hPbhu18G9 # oxw0sBi51T0Tb+N6lOVVSfmiEZWLXRq+lDCZdV0j864brsSjo4x8VEGrLaFTOJLf # X4MW6vBI4Pcb7EGnHjj5WvRKsf8gdahdx8bSTjORIm8oGri9Iyw6Vrg2khuhjnuH # 99sD1O06cvrylp+sCOVei8H3S6/xCepQXUXnCBCd1/cetgV+olo+ZR78Z8ZjXPED # jhZ23lsDcge+4W141lsCiwLgzI0YO3Ac+84zQLIvcx16c8zow3G9FO9sTlBSsgnW # 0XJrsUF7AZB6quUSMytG7WK+OBizzCRwj7ItC+Mty68wLrei5lDVj8b0t8hAQEdr # dOb7jku+Dz8OspGZx1aDKKifGDO+Ppv4PjAM2G44OmkM824SvvFg8+FEr9NgbKbp # VgTZDCeVC6IEpzthKsK8WeompLo7Sc33KITqwMbGiyGs+gsnmgKP2bcTLF8YTlFk # dqFBWjo3tjH5oukgTLCSYY4xPaHR9q418vGAfRox15GtUVliQ9iL5oH47PVXg4U7 # YsNZ74nD1pUueg== # =Umli # -----END PGP SIGNATURE----- # gpg: Signature made Fri 24 Feb 2023 18:49:35 GMT # gpg: using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmerdabbelt@google.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 # Subkey fingerprint: 2B3C 3747 4468 43B2 4A94 3A7A 2E13 19F3 5FBB 1889 * tag 'pull-riscv-to-apply-20230224' of github.com:palmer-dabbelt/qemu: target/riscv: Fix vslide1up.vf and vslide1down.vf target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state() target/riscv: Smepmp: Skip applying default rules when address matches MAINTAINERS: Add some RISC-V reviewers target/riscv: Remove privileged spec version restriction for RVV hw/riscv/boot.c: make riscv_load_initrd() static hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-24Merge tag 'pull-error-2023-02-23' of https://repo.or.cz/qemu/armbru into stagingPeter Maydell
Error reporting patches patches for 2023-02-23 # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEENUvIs9frKmtoZ05fOHC0AOuRhlMFAmP3ZogSHGFybWJydUBy # ZWRoYXQuY29tAAoJEDhwtADrkYZT+PsP/ibioHJkJiR8yMt2/2iSwpkMrphZDmRQ # 5sAgxCARdcp0m7maH4McCFkgtERcROip+j98FV29qI4y2P/mLkt1jyMYC+TH9r4O # X3G997526gzZBLIJJsnYlVlJ1Gbgn+uCy4AzRLuhaKAHsYoxkP0jygoSs/eIZ9tK # Wg2tkQ/wY4bXihrlzdOpWqU3Y0ADo2PQ29p7HWheRMDQz6JQxq82hFFs1jgGQ1aq # 4HmcpIMX0+/LshFbDU91dL1pxW17vWT9J3xtzAsWlfBBgAh257LKvJqVD0XojL04 # FxJZ05IqTXZ04gvwgji0dcvNjdmP/dXVoGLfxAYwCFtKxiig700bdNb0+6MjCT6u # P2tSPyQQzNQ5LYI7AgER4kMyXK22RkBXx+Q7y7QK1YXszWWSmGFZWGLA2FSg4lO6 # 5jsCgtEGixsMym/ox3XeoywSh4BgWkNXC+gKMSg/hQXgfriQmndHUOlK0ZU95I43 # 7gnPol+pU1HIEy/GDU8oMyieG513Ti1KVPZyv/FbuW75AYUDlHAXH/5OFlsuaLIR # 1QF449xCLR5vIOOLXHbKJ9jbkcAaidhq5pOhLr7oV3yKh4H53iNB7gy8+vJ6XtBf # tXXcYPVD8LpZxDegKNpIaeT0Nr4pyy6bYfrF+YeisVotD6PDtPALfJ9eSCWjaQsl # DG2opOfv5xuV # =VRxu # -----END PGP SIGNATURE----- # gpg: Signature made Thu 23 Feb 2023 13:13:44 GMT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * tag 'pull-error-2023-02-23' of https://repo.or.cz/qemu/armbru: rocker: Tweak stubbed out monitor commands' error messages migration/colo: Improve an x-colo-lost-heartbeat error message hw/core: Improve the query-hotpluggable-cpus error message replay: Simplify setting replay blockers qga: Drop dangling reference to QERR_QGA_LOGGING_DISABLED hw/acpi: Move QMP command to hw/core/ hw/acpi: Dumb down acpi_table_add() stub hw/smbios: Dumb down smbios_entry_add() stub hw/core: Improve error message when machine doesn't provide NMIs dump: Assert cpu_get_note_size() can't fail dump: Improve error message when target doesn't support memory dump error: Drop superfluous #include "qapi/qmp/qerror.h" Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-24Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell
* x86 bugfixes * OpenBSD support for naming threads * Refined Python support policy # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmP0wtkUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroNI6QgAjMvEV0N5FZYMpiuQdjebBeV+uHM6 # LThewCQa0cW5jb1X1NFBbOxYlNfE3WQeZqQF+BiVJr5wT2UsyNsPH7wTjsP387vV # juoD7D/XZo8P4Qi+vJWo8XVBrzWEK8QS1P+NxWr+ZnsAhDx2+MR87fVmHtVBW1pI # oDO0iyRrvVtaTAIVyNWSgZ59SLMmcH/6L4aYv5nrKYuAWx7fTneGGheKuqk55RsV # sMv+fHolmmwKVm8tMFksw0atPwL7ZmSm1uObNHCQKdDNSoakC7YpaXa3y8LEzU7I # B4h/PsmRpN33ggvsiuzFp9kfEHMy4QazfpoVFFqTLalhTr+XuiNTxj8xdA== # =6eNN # -----END PGP SIGNATURE----- # gpg: Signature made Tue 21 Feb 2023 13:10:49 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: target/i386/gdbstub: Fix a bug about order of FPU stack in 'g' packets. docs: build-platforms: refine requirements on Python build dependencies thread-posix: add support for setting threads name on OpenBSD target/i386: Fix 32-bit AD[CO]X insns in 64-bit mode Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-23target/riscv: Fix vslide1up.vf and vslide1down.vfLIU Zhiwei
vslide1up_##BITWIDTH is used by the vslide1up.vx and vslide1up.vf. So its scalar input should be uint64_t to hold the 64 bits float register.And the same for vslide1down_##BITWIDTH. This bug is caught when run these instructions on qemu-riscv32. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-ID: <20230213094550.29621-1-zhiwei_liu@linux.alibaba.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-02-23target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()Daniel Henrique Barboza
We have a RISCVCPU *cpu pointer available at the start of the function. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-ID: <20230210123836.506286-1-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-02-23target/riscv: Smepmp: Skip applying default rules when address matchesHimanshu Chauhan
When MSECCFG.MML is set, after checking the address range in PMP if the asked permissions are not same as programmed in PMP, the default permissions are applied. This should only be the case when there is no matching address is found. This patch skips applying default rules when matching address range is found. It returns the index of the match PMP entry. Fixes: 824cac681c3 (target/riscv: Fix PMP propagation for tlb) Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230209055206.229392-1-hchauhan@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-02-23target/riscv: Remove privileged spec version restriction for RVVFrank Chang
The RVV specification does not require that the core needs to support the privileged specification v1.12.0 to support RVV, and there is no dependency from ISA level. This commit removes the restriction from both RVV CSRs and extension CPU ISA string. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230208063209.27279-1-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-02-23error: Drop superfluous #include "qapi/qmp/qerror.h"Markus Armbruster
Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20230207075115.1525-2-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com>
2023-02-21target/microblaze: Add gdbstub xmlRichard Henderson
Mirroring the upstream gdb xml files, the two stack boundary registers are separated out. Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-02-21target/i386/gdbstub: Fix a bug about order of FPU stack in 'g' packets.TaiseiIto
Before this commit, when GDB attached an OS working on QEMU, order of FPU stack registers printed by GDB command 'info float' was wrong. There was a bug causing the problem in 'g' packets sent by QEMU to GDB. The packets have values of registers of machine emulated by QEMU containing FPU stack registers. There are 2 ways to specify a x87 FPU stack register. The first is specifying by absolute indexed register names (R0, ..., R7). The second is specifying by stack top relative indexed register names (ST0, ..., ST7). Values of the FPU stack registers should be located in 'g' packet and be ordered by the relative index. But QEMU had located these registers ordered by the absolute index. After this commit, when QEMU reads registers to make a 'g' packet, QEMU specifies FPU stack registers by the relative index. Then, the registers are ordered correctly in the packet. As a result, GDB, the packet receiver, can print FPU stack registers in the correct order. Signed-off-by: TaiseiIto <taisei1212@outlook.jp> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <TY0PR0101MB4285923FBE9AD97CE832D95BA4E59@TY0PR0101MB4285.apcprd01.prod.exchangelabs.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-02-16target/arm: Move cpregs code out of cpu.hFabiano Rosas
Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have a cpregs.h header which is more suitable for this code. Code moved verbatim. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-16target/arm: Move PC alignment checkFabiano Rosas
Move this earlier to make the next patch diff cleaner. While here update the comment slightly to not give the impression that the misalignment affects only TCG. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Fabiano Rosas <farosas@suse.de> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-16target/arm: wrap call to aarch64_sve_change_el in tcg_enabled()Claudio Fontana
Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fabiano Rosas <farosas@suse.de> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-16target/arm: wrap psci call with tcg_enabledClaudio Fontana
for "all" builds (tcg + kvm), we want to avoid doing the psci check if tcg is built-in, but not enabled. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fabiano Rosas <farosas@suse.de> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-16target/arm: rename handle_semihosting to tcg_handle_semihostingClaudio Fontana
make it clearer from the name that this is a tcg-only function. Signed-off-by: Claudio Fontana <cfontana@suse.de> Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-16target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h'Philippe Mathieu-Daudé
While dozens of files include "cpu.h", only 3 files require these NVIC helper declarations. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230206223502.25122-12-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-16target/arm: Store CPUARMState::nvic as NVICState*Philippe Mathieu-Daudé
There is no point in using a void pointer to access the NVIC. Use the real type to avoid casting it while debugging. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230206223502.25122-11-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-16target/arm: Restrict CPUARMState::nvic to sysemuPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230206223502.25122-10-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-16target/arm: Restrict CPUARMState::arm_boot_info to sysemuPhilippe Mathieu-Daudé
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230206223502.25122-9-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-16target/arm: Restrict CPUARMState::gicv3state to sysemuPhilippe Mathieu-Daudé
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230206223502.25122-8-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-16target/arm: Avoid resetting CPUARMState::eabi fieldPhilippe Mathieu-Daudé
Although the 'eabi' field is only used in user emulation where CPU reset doesn't occur, it doesn't belong to the area to reset. Move it after the 'end_reset_fields' for consistency. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230206223502.25122-7-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-16target/arm: Convert CPUARMState::eabi to booleanPhilippe Mathieu-Daudé
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230206223502.25122-6-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-16target/arm: Constify ID_PFR1 on user emulationPhilippe Mathieu-Daudé
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230206223502.25122-5-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-16target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scopePhilippe Mathieu-Daudé
arm_v7m_mmu_idx_all() and arm_v7m_mmu_idx_for_secstate_and_priv() are only used for system emulation in m_helper.c. Move the definitions to avoid prototype forward declarations. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230206223502.25122-4-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-16target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulationPhilippe Mathieu-Daudé
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230206223502.25122-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-16target/i386: Fix 32-bit AD[CO]X insns in 64-bit modeRichard Henderson
Failure to truncate the inputs results in garbage for the carry-out. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1373 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230115012103.3131796-1-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-02-11target/i386: fix ADOX followed by ADCXPaolo Bonzini
When ADCX is followed by ADOX or vice versa, the second instruction's carry comes from EFLAGS and the condition codes use the CC_OP_ADCOX operation. Retrieving the carry from EFLAGS is handled by this bit of gen_ADCOX: tcg_gen_extract_tl(carry_in, cpu_cc_src, ctz32(cc_op == CC_OP_ADCX ? CC_C : CC_O), 1); Unfortunately, in this case cc_op has been overwritten by the previous "if" statement to CC_OP_ADCOX. This works by chance when the first instruction is ADCX; however, if the first instruction is ADOX, ADCX will incorrectly take its carry from OF instead of CF. Fix by moving the computation of the new cc_op at the end of the function. The included exhaustive test case fails without this patch and passes afterwards. Because ADCX/ADOX need not be invoked through the VEX prefix, this regression bisects to commit 16fc5726a6e2 ("target/i386: reimplement 0x0f 0x38, add AVX", 2022-10-18). However, the mistake happened a little earlier, when BMI instructions were rewritten using the new decoder framework. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1471 Reported-by: Paul Jolly <https://gitlab.com/myitcv> Fixes: 1d0b926150e5 ("target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder", 2022-10-18) Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-02-11target/i386: Fix C flag for BLSI, BLSMSK, BLSRRichard Henderson
We forgot to set cc_src, which is used for computing C. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1370 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230114180601.2993644-1-richard.henderson@linaro.org> Cc: qemu-stable@nongnu.org Fixes: 1d0b926150e5 ("target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder", 2022-10-18) Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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