aboutsummaryrefslogtreecommitdiff
path: root/target
AgeCommit message (Expand)Author
2021-10-23Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.2-pull...Richard Henderson
2021-10-22disas/nios2: Simplify endianess conversionPhilippe Mathieu-Daudé
2021-10-22target/riscv: Compute mstatus.sd on demandRichard Henderson
2021-10-22target/riscv: Use riscv_csrrw_debug for cpu_dumpRichard Henderson
2021-10-22target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson
2021-10-22target/riscv: Use gen_unary_per_ol for RVBRichard Henderson
2021-10-22target/riscv: Adjust trans_rev8_32 for riscv64Richard Henderson
2021-10-22target/riscv: Use gen_arith_per_ol for RVMRichard Henderson
2021-10-22target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson
2021-10-22target/riscv: Replace is_32bit with get_xl/get_xlenRichard Henderson
2021-10-22target/riscv: Properly check SEW in amo_opRichard Henderson
2021-10-22target/riscv: Use REQUIRE_64BIT in amo_check64Richard Henderson
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson
2021-10-22target/riscv: Create RISCVMXL enumerationRichard Henderson
2021-10-22target/riscv: Move cpu_get_tb_cpu_state out of lineRichard Henderson
2021-10-22target/riscv: Organise the CPU propertiesAlistair Francis
2021-10-22target/riscv: Remove some unused macrosAlistair Francis
2021-10-22target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvhFrank Chang
2021-10-22target/riscv: Fix orc.b implementationPhilipp Tomsich
2021-10-22target/riscv: line up all of the registers in the info register dumpTravis Geiselbrecht
2021-10-22target/riscv: Pass the same value to oprsz and maxsz for vmv.v.vFrank Chang
2021-10-21target/ppc: adding user read/write functions for PMCsDaniel Henrique Barboza
2021-10-21target/ppc: add user read/write functions for MMCR2Daniel Henrique Barboza
2021-10-21target/ppc: add user read/write functions for MMCR0Gustavo Romero
2021-10-21target/ppc: add MMCR0 PMCC bits to hflagsDaniel Henrique Barboza
2021-10-21target/ppc: Filter mtmsr[d] input before setting MSRMatheus Ferst
2021-10-21target/ppc: Fix XER access in monitorMatheus Ferst
2021-10-21linux-user: Fix XER access in ppc version of elf_core_copy_regsMatheus Ferst
2021-10-21target/ppc: Fix XER access in gdbstubMatheus Ferst
2021-10-21target/ppc: Use tcg_constant_i64() in gen_brh()Philippe Mathieu-Daudé
2021-10-21target/ppc: Use tcg_constant_i32() in gen_setb()Philippe Mathieu-Daudé
2021-10-18target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn()Philippe Mathieu-Daudé
2021-10-18target/mips: Fix DEXTRV_S.H DSP opcodePhilippe Mathieu-Daudé
2021-10-18target/mips: Use tcg_constant_tl() in gen_compute_compact_branch()Philippe Mathieu-Daudé
2021-10-18target/mips: Use explicit extract32() calls in gen_msa_i5()Philippe Mathieu-Daudé
2021-10-18target/mips: Use tcg_constant_i32() in gen_msa_3rf()Philippe Mathieu-Daudé
2021-10-18target/mips: Use tcg_constant_i32() in gen_msa_2r()Philippe Mathieu-Daudé
2021-10-18target/mips: Use tcg_constant_i32() in gen_msa_2rf()Philippe Mathieu-Daudé
2021-10-18target/mips: Use tcg_constant_i32() in gen_msa_elm_df()Philippe Mathieu-Daudé
2021-10-18target/mips: Remove unused register from MSA 2R/2RF instruction formatPhilippe Mathieu-Daudé
2021-10-17target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6Philippe Mathieu-Daudé
2021-10-15target/xtensa: Drop check for singlestep_enabledRichard Henderson
2021-10-15target/tricore: Drop check for singlestep_enabledRichard Henderson
2021-10-15target/sh4: Drop check for singlestep_enabledRichard Henderson
2021-10-15target/s390x: Drop check for singlestep_enabledRichard Henderson
2021-10-15target/rx: Drop checks for singlestep_enabledRichard Henderson
2021-10-15target/riscv: Remove exit_tb and lookup_and_goto_ptrRichard Henderson
2021-10-15target/riscv: Remove dead code after exceptionRichard Henderson