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2017-01-16Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-2.9-pull-request' ↵Peter Maydell
into staging # gpg: Signature made Sat 14 Jan 2017 09:06:31 GMT # gpg: using RSA key 0xF30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-for-2.9-pull-request: target-m68k: increment/decrement with SP target-m68k: CAS doesn't need aligned access target-m68k: manage pre-dec et post-inc in CAS target-m68k: fix gen_flush_flags() target-m68k: fix bit operation with immediate value m68k: Remove PCI and USB from config file target-m68k: Implement bfffo target-m68k: Implement bitfield ops for memory target-m68k: Implement bitfield ops for registers Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-14target-m68k: increment/decrement with SPLaurent Vivier
On 680x0 family only. Address Register indirect With postincrement: When using the stack pointer (A7) with byte size data, the register is incremented by two. Address Register indirect With predecrement: When using the stack pointer (A7) with byte size data, the register is decremented by two. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1484332593-16782-6-git-send-email-laurent@vivier.eu>
2017-01-14target-m68k: CAS doesn't need aligned accessLaurent Vivier
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1484332593-16782-5-git-send-email-laurent@vivier.eu>
2017-01-14target-m68k: manage pre-dec et post-inc in CASLaurent Vivier
In these cases we must update the address register after the operation. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1484332593-16782-4-git-send-email-laurent@vivier.eu>
2017-01-14target-m68k: fix gen_flush_flags()Laurent Vivier
gen_flush_flags() is setting unconditionally cc_op_synced to 1 and s->cc_op to CC_OP_FLAGS, whereas env->cc_op can be set to something else by a previous tcg fragment. We fix that by not setting cc_op_synced to 1 (except for gen_helper_flush_flags() that updates env->cc_op) FIX: https://github.com/vivier/qemu-m68k/issues/19 Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1484332593-16782-3-git-send-email-laurent@vivier.eu>
2017-01-14target-m68k: fix bit operation with immediate valueLaurent Vivier
M680x0 bit operations with an immediate value use 9 bits of the 16bit value, while coldfire ones use only 8 bits. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1484332593-16782-2-git-send-email-laurent@vivier.eu>
2017-01-14target-m68k: Implement bfffoRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1479242669-25852-1-git-send-email-rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-01-14target-m68k: Implement bitfield ops for memoryRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1478699171-10637-6-git-send-email-rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-01-14target-m68k: Implement bitfield ops for registersRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1478699171-10637-5-git-send-email-rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-01-13target/arm: Fix ubfx et al for aarch64Richard Henderson
The patch in 59a71b4c5b4e suffered from a merge failure when compared to the original patch in http://lists.nongnu.org/archive/html/qemu-devel/2016-12/msg00137.html Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-13Merge remote-tracking branch ↵Peter Maydell
'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging x86 and machine queue, 2017-01-17 Includes i386, CPU, NUMA, and memory backends changes. i386: target/i386: Fix bad patch application to translate.c CPU: qmp: Report QOM type name on query-cpu-definitions NUMA: numa: make -numa parser dynamically allocate CPUs masks Memory backends: qom: remove unused header monitor: reuse user_creatable_add_opts() instead of user_creatable_add() monitor: fix qmp/hmp query-memdev not reporting IDs of memory backends # gpg: Signature made Thu 12 Jan 2017 17:53:11 GMT # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-and-machine-pull-request: qmp: Report QOM type name on query-cpu-definitions numa: make -numa parser dynamically allocate CPUs masks target/i386: Fix bad patch application to translate.c monitor: fix qmp/hmp query-memdev not reporting IDs of memory backends monitor: reuse user_creatable_add_opts() instead of user_creatable_add() qom: remove unused header Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-12Merge remote-tracking branch ↵Peter Maydell
'remotes/bkoppelmann/tags/pull-tricore-2017-01-11-2' into staging TriCore FPU patches # gpg: Signature made Wed 11 Jan 2017 13:40:11 GMT # gpg: using RSA key 0x0AD2C6396B69CA14 # gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" # Primary key fingerprint: 6E63 6A7E 83F2 DD0C FA6E 6E37 0AD2 C639 6B69 CA14 * remotes/bkoppelmann/tags/pull-tricore-2017-01-11-2: target-tricore: Add updfl instruction target-tricore: Added new JNE instruction variant target-tricore: Added new MOV instruction variant target-tricore: Added MADD.F and MSUB.F instructions target-tricore: Added FTOUZ instruction Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-12qmp: Report QOM type name on query-cpu-definitionsEduardo Habkost
The new typename attribute on query-cpu-definitions will be used to help management software use device-list-properties to check which properties can be set using -cpu or -global for the CPU model. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1479320499-29818-1-git-send-email-ehabkost@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-01-12target/i386: Fix bad patch application to translate.cDoug Evans
In commit c52ab08aee6f7d4717fc6b517174043126bd302f, the patch snippet for the "syscall" insn got applied to "iret". Signed-off-by: Doug Evans <dje@google.com> Message-Id: <f403045cde4049058c05446d5c04@google.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-01-11target-tricore: Add updfl instructionBastian Koppelmann
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-11target-tricore: Added new JNE instruction variantPeer Adelt
If D[15] is != sign_ext(const4) then PC will be set to (PC + zero_ext(disp4 + 16)). [BK: fixed style errors] Signed-off-by: Peer Adelt <peer.adelt@c-lab.de> Message-Id: <1465314555-11501-5-git-send-email-peer.adelt@c-lab.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2017-01-11target-tricore: Added new MOV instruction variantPeer Adelt
Puts the content of data register D[a] into E[c][63:32] and the content of data register D[b] into E[c][31:0]. [BK: fix style error] [BK: Allocate temporaries only when needed] Signed-off-by: Peer Adelt <peer.adelt@c-lab.de> Message-Id: <1465314555-11501-4-git-send-email-peer.adelt@c-lab.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2017-01-11target-tricore: Added MADD.F and MSUB.F instructionsBastian Koppelmann
Multiplies D[a] and D[b] and adds/subtracts the result to/from D[d]. The result is put in D[c]. All operands are floating-point numbers. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-11target-tricore: Added FTOUZ instructionBastian Koppelmann
Converts a 32-bit floating point number to an unsigned int. The result is rounded towards zero. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-i386: Use ctpop helperRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-tilegx: Use ctpop helperRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-sparc: Use ctpop helperRichard Henderson
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-s390x: Avoid a loop for popcntRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-ppc: Use ctpop helperRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-alpha: Use ctpop helperRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-xtensa: Use clrsb helperRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-tricore: Use clrsb helperRichard Henderson
Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-arm: Use clrsb helperRichard Henderson
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-i386: Use clz and ctz opcodesRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-arm: Use clz opcodeRichard Henderson
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-xtensa: Use clz opcodeRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-unicore32: Use clz opcodeRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-tricore: Use clz opcodeRichard Henderson
Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-tilegx: Use clz and ctz opcodesRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-s390x: Use clz opcodeRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-ppc: Use clz and ctz opcodesRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-openrisc: Use clz and ctz opcodesRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-mips: Use clz opcodeRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-microblaze: Use clz opcodeRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-cris: Use clz opcodeRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-alpha: Use the ctz and clz opcodesRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-s390x: Use the new deposit and extract opsRichard Henderson
Use the new primitives for RISBG. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-ppc: Use the new deposit and extract opsRichard Henderson
Use the new primitives for RDWINM and RLDICL. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-mips: Use the new extract opRichard Henderson
Use extract for EXT and DEXT. Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-i386: Use new deposit and extract opsRichard Henderson
A couple of places where it was easy to identify a right-shift followed by an extract or and-with-immediate, and the obvious sign-extract from a high byte register. Acked-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-arm: Use new deposit and extract opsRichard Henderson
Use the new primitives for UBFX and SBFX. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-alpha: Use deposit and extract opsRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-12-28Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-2.9-pull-request' ↵Peter Maydell
into staging # gpg: Signature made Tue 27 Dec 2016 17:52:12 GMT # gpg: using RSA key 0xF30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-for-2.9-pull-request: target-m68k: free TCG variables that are not target-m68k: add rol/ror/roxl/roxr instructions target-m68k: Inline shifts target-m68k: Do not cpu_abort on undefined insns target-m68k: Implement 680x0 movem target-m68k: add cas/cas2 ops target-m68k: add abcd/sbcd/nbcd target-m68k: add 680x0 divu/divs variants target-m68k: add 64bit mull target-m68k: add cmpm target-m68k: Split gen_lea and gen_ea target-m68k: Delay autoinc writeback Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27target-m68k: free TCG variables that are notLaurent Vivier
This is a cleanup patch. It adds call to tcg_temp_free() when it is missing. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-12-27target-m68k: add rol/ror/roxl/roxr instructionsLaurent Vivier
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-23 13:10:22 +0000