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AgeCommit message (Expand)Author
2021-06-24target/riscv: gdbstub: Fix dynamic CSR XML generationBin Meng
2021-06-24target/riscv: Use target_ulong for the DisasContext misaAlistair Francis
2021-06-22Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s390x-20210621' into...Peter Maydell
2021-06-22Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210619-2' in...Peter Maydell
2021-06-21Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request'...Peter Maydell
2021-06-21target/s390x: Use s390_cpu_{set_psw, get_psw_mask} in gdbstubRichard Henderson
2021-06-21target/s390x: Improve s390_cpu_dump_state vs cc_opRichard Henderson
2021-06-21target/s390x: Do not modify cpu state in s390_cpu_get_psw_maskRichard Henderson
2021-06-21target/s390x: Expose load_psw and get_psw_mask to cpu.hRichard Henderson
2021-06-21s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z14 GA2David Hildenbrand
2021-06-21s390x/tcg: We support Vector enhancements facilityDavid Hildenbrand
2021-06-21s390x/tcg: Implement VECTOR FP (MAXIMUM|MINIMUM)David Hildenbrand
2021-06-21s390x/tcg: Implement VECTOR FP NEGATIVE MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS IMMEDIATEDavid Hildenbrand
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP PERFORM SIGN OPERATIONDavid Hildenbrand
2021-06-21s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDEDDavid Hildenbrand
2021-06-21s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENEDDavid Hildenbrand
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE (AND SIGNAL) SCALARDavid Hildenbrand
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE *David Hildenbrand
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR (LOAD FP INTEGER|FP SQUARE ROOT)David Hildenbrand
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP (ADD|DIVIDE|MULTIPLY|SUBTRACT)David Hildenbrand
2021-06-21s390x/tcg: Implement VECTOR MULTIPLY SUM LOGICALDavid Hildenbrand
2021-06-21s390x/tcg: Implement VECTOR BIT PERMUTEDavid Hildenbrand
2021-06-21s390x/tcg: Simplify wfc64() handlingDavid Hildenbrand
2021-06-21s390x/tcg: Simplify vflr64() handlingDavid Hildenbrand
2021-06-21s390x/tcg: Simplify vfll32() handlingDavid Hildenbrand
2021-06-21s390x/tcg: Simplify vfma64() handlingDavid Hildenbrand
2021-06-21s390x/tcg: Simplify vftci64() handlingDavid Hildenbrand
2021-06-21s390x/tcg: Simplify vfc64() handlingDavid Hildenbrand
2021-06-21s390x/tcg: Simplify vop64_2() handlingDavid Hildenbrand
2021-06-21s390x/tcg: Simplify vop64_3() handlingDavid Hildenbrand
2021-06-21s390x/tcg: Fix instruction name for VECTOR FP LOAD (LENGTHENED|ROUNDED)David Hildenbrand
2021-06-21s390x/tcg: Fix FP CONVERT TO (LOGICAL) FIXED NaN handlingDavid Hildenbrand
2021-06-21s390x/kvm: remove unused gs handlingCornelia Huck
2021-06-19tcg: Combine dh_is_64bit and dh_is_signed to dh_typecodeRichard Henderson
2021-06-17i386: Add ratelimit for bus locks acquired in guestChenyi Qiang
2021-06-17Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...Peter Maydell
2021-06-16bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operationsPeter Maydell
2021-06-16target/arm: Move expand_pred_b() data to vec_helper.cPeter Maydell
2021-06-16target/arm: Add framework for MVE decodePeter Maydell
2021-06-16target/arm: Implement MVE LETP insnPeter Maydell
2021-06-16target/arm: Implement MVE DLSTPPeter Maydell
2021-06-16target/arm: Implement MVE WLSTP insnPeter Maydell
2021-06-16target/arm: Implement MVE LCTPPeter Maydell
2021-06-16target/arm: Let vfp_access_check() handle late NOCP checksPeter Maydell
2021-06-16target/arm: Add handling for PSR.ECI/ICIPeter Maydell
2021-06-16target/arm: Handle VPR semantics in existing codePeter Maydell
2021-06-16target/arm: Enable FPSCR.QC bit for MVEPeter Maydell
2021-06-16target/arm: Provide and use H8 and H1_8 macrosPeter Maydell
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