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2017-07-25s390x/css: fix ilen in IO instruction handlersHalil Pasic
When initiating a program check interruption by calling program_interrupt the instruction length (ilen) of the current instruction is supplied as the third parameter. On s390x all the IO instructions are of instruction format S and their ilen is 4. The calls to program_interrupt (introduced by commits 7b18aad543 ("s390: Add channel I/O instructions.", 2013-01-24) and 61bf0dcb2e ("s390x/ioinst: Add missing alignment checks for IO instructions", 2013-06-21)) however use ilen == 2. This is probably due to a confusion between ilen which specifies the instruction length in bytes and ILC which does the same but in halfwords. If kvm_enabled() this does not actually matter, because the ilen parameter of program_interrupt is effectively unused. Let's provide the correct ilen to program_interrupt. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Fixes: 7b18aad543 ("s390: Add channel I/O instructions.") Fixes: 61bf0dcb2e ("s390x/ioinst: Add missing alignment checks for IO instructions") Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20170724143452.55534-1-pasic@linux.vnet.ibm.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-07-25target/s390x: Add remaining switches to compile with --disable-tcgThomas Huth
Adding some CONFIG_TCG tests to be finally able to compile QEMU on s390x also without TCG. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1500886370-14572-6-git-send-email-thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-07-25target/s390x: Move exception-related functions to a new excp_helper.c fileThomas Huth
These functions can not be compiled with --disable-tcg. But since we need the other functions from helper.c in the non-tcg build, we can also not simply remove helper.c from the non-tcg builds. Thus the problematic functions have to be moved into a separate new file instead that we can later omit in the non-tcg builds. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1500886370-14572-5-git-send-email-thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-07-25target/s390x: Rework program_interrupt() and related functionsThomas Huth
misc_helper.c won't be compiled with --disable-tcg anymore, but we still need the program_interrupt() function in that case. Move it to interrupt.c instead, and refactor it to re-use the code from trigger_pgm_exception() (for TCG) and enter_pgmcheck() (for KVM, which now got renamed to kvm_s390_program_interrupt() for clarity). Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1500886370-14572-4-git-send-email-thuth@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-07-25target/s390x: Move diag helpers to a separate fileThomas Huth
misc_helper.c won't be compiled with --disable-tcg anymore, but we still need the diag helpers in KVM builds, too, so move the helper functions to a separate file. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1500886370-14572-3-git-send-email-thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-07-25target/s390x: Move s390_cpu_dump_state() to helper.cThomas Huth
translate.c can not be compiled with --disable-tcg, but we need the s390_cpu_dump_state() in KVM-only builds, too. So let's move that function to helper.c instead, which will also be compiled when --disable-tcg has been specified. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1500886370-14572-2-git-send-email-thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-07-25target/s390x: improve baselining if certain base features are missingDavid Hildenbrand
There are certain features that we put into base models, but that are not relevant for the actual search. The most famous example are MSA subfunctions that might be disabled on certain real hardware out there. While the kvm host model detection will usually detect the correct model on such machines (as it will in the common case not pass features to check for into s390_find_cpu_def()), baselining will fall back to a quite old model just because some MSA subfunctions are missing. Let's improve that by ignoring lack of these features while performing the search for a base model. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170720123721.12366-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-07-25s390x/kvm: better comment regarding zPCI feature availabilityDavid Hildenbrand
Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170720123721.12366-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-07-25target/s390x: introduce (test|set)_be_bitDavid Hildenbrand
Using ordinary bitmap operations to set/test bits does not work properly on architectures !s390x. Let's drop (test|set)_bit_inv and introduce (test|set)_be_bit instead. These functions work on uint8_t array, not on unsigned longs arrays and are for now only used in the context of CPU features. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170720123721.12366-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-07-25target/s390x: indicate query subfunction in s390_fill_feat_blockDavid Hildenbrand
We'll have to do the same for TCG, so let's just move it in there. Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170720123721.12366-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-07-25target/s390x: drop BE_BIT()David Hildenbrand
Unused and broken, let's just get rid of it. Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170720123721.12366-2-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-07-25s390/cpumodel: remove KSS from the default model of z14Christian Borntraeger
The SIE_KSS feature will allow a guest to use KSS for a nested guest. To create a nested guest the SIE_F2 facility is still necessary. Since SIE_F2 is not part of the default model it does not make a lot of sense to provide the SIE_KSS feature in the default model. Let's also create a dependency check. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Jason J. Herne <jjherne@linux.vnet.ibm.com> Reviewed-by: Janosch Frank <frankja@linux.vnet.ibm.com> Message-Id: <1500550051-7821-2-git-send-email-borntraeger@de.ibm.com> Acked-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-07-24target/arm: fix TCG temp leak in aarch64 rev16Emilio G. Cota
Fix a TCG temporary leak in the new aarch64 rev16 handling. Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-24qapi: Use QNull for a more regular visit_type_null()Markus Armbruster
Make visit_type_null() take an @obj argument like its buddies. This helps keep the next commit simple. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Daniel P. Berrange <berrange@redhat.com>
2017-07-24qapi: Separate type QNull from QObjectMarkus Armbruster
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Daniel P. Berrange <berrange@redhat.com>
2017-07-21Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170721' into stagingPeter Maydell
MIPS patches 2017-07-21 Changes: * Add Enhanced Virtual Addressing (EVA) support # gpg: Signature made Fri 21 Jul 2017 03:25:15 BST # gpg: using RSA key 0x2238EB86D5F797C2 # gpg: Good signature from "Yongbok Kim <yongbok.kim@imgtec.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8600 4CF5 3415 A5D9 4CFA 2B5C 2238 EB86 D5F7 97C2 * remotes/yongbok/tags/mips-20170721: target/mips: Enable CP0_EBase.WG on MIPS64 CPUs target/mips: Add EVA support to P5600 target/mips: Implement segmentation control target/mips: Add segmentation control registers target/mips: Add an MMU mode for ERL target/mips: Abstract mmu_idx from hflags target/mips: Check memory permissions with mem_idx target/mips: Decode microMIPS EVA load & store instructions target/mips: Decode MIPS32 EVA load & store instructions target/mips: Prepare loads/stores for EVA target/mips: Add CP0_Ebase.WG (write gate) support target/mips: Weaken TLB flush on UX,SX,KX,ASID changes target/mips: Fix TLBWI shadow flush for EHINV,XI,RI target/mips: Fix MIPS64 MFC0 UserLocal on BE host Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-21Use qemu_tolower() and qemu_toupper(), not tolower() and toupper()Peter Maydell
On NetBSD, where tolower() and toupper() are implemented using an array lookup, the compiler warns if you pass a plain 'char' to these functions: gdbstub.c:914:13: warning: array subscript has type 'char' This reflects the fact that toupper() and tolower() give undefined behaviour if they are passed a value that isn't a valid 'unsigned char' or EOF. We have qemu_tolower() and qemu_toupper() to avoid this problem; use them. (The use in scsi-generic.c does not trigger the warning because it passes a uint8_t; we switch it anyway, for consistency.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> for the s390 part. Acked-by: David Gibson <david@gibson.dropbear.id.au> Message-id: 1500568290-7966-1-git-send-email-peter.maydell@linaro.org
2017-07-21target/mips: Enable CP0_EBase.WG on MIPS64 CPUsJames Hogan
Enable the CP0_EBase.WG (write gate) on the I6400 and MIPS64R2-generic CPUs. This allows 64-bit guests to run KVM itself, which uses CP0_EBase.WG to point CP0_EBase at XKPhys. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-21target/mips: Add EVA support to P5600James Hogan
Add the Enhanced Virtual Addressing (EVA) feature to the P5600 core configuration, along with the related Segmentation Control (SC) feature and writable CP0_EBase.WG bit. This allows it to run Malta EVA kernels. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Implement segmentation controlJames Hogan
Implement the optional segmentation control feature in the virtual to physical address translation code. The fixed legacy segment and xkphys handling is replaced with a dynamic layout based on the segmentation control registers (which should be set up even when the feature is not exposed to the guest). Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> [yongbok.kim@imgtec.com: cosmetic changes] Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Add segmentation control registersJames Hogan
The optional segmentation control registers CP0_SegCtl0, CP0_SegCtl1 & CP0_SegCtl2 control the behaviour and required privilege of the legacy virtual memory segments. Add them to the CP0 interface so they can be read and written when CP0_Config3.SC=1, and initialise them to describe the standard legacy layout so they can be used in future patches regardless of whether they are exposed to the guest. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Add an MMU mode for ERLJames Hogan
The segmentation control feature allows a legacy memory segment to become unmapped uncached at error level (according to CP0_Status.ERL), and in fact the user segment is already treated in this way by QEMU. Add a new MMU mode for this state so that QEMU's mappings don't persist between ERL=0 and ERL=1. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> [yongbok.kim@imgtec.com: cosmetic changes] Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Abstract mmu_idx from hflagsJames Hogan
The MIPS mmu_idx is sometimes calculated from hflags without an env pointer available as cpu_mmu_index() requires. Create a common hflags_mmu_index() for the purpose of this calculation which can operate on any hflags, not just with an env pointer, and update cpu_mmu_index() itself and gen_intermediate_code() to use it. Also update debug_post_eret() and helper_mtc0_status() to log the MMU mode with the status change (SM, UM, or nothing for kernel mode) based on cpu_mmu_index() rather than directly testing hflags. This will also allow the logic to be more easily updated when a new MMU mode is added. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Check memory permissions with mem_idxJames Hogan
When performing virtual to physical address translation, check the required privilege level based on the mem_idx rather than the mode in the hflags. This will allow EVA loads & stores to operate safely only on user memory from kernel mode. For the cases where the mmu_idx doesn't need to be overridden (mips_cpu_get_phys_page_debug() and cpu_mips_translate_address()), we calculate the required mmu_idx using cpu_mmu_index(). Note that this only tests the MIPS_HFLAG_KSU bits rather than MIPS_HFLAG_MODE, so we don't test the debug mode hflag MIPS_HFLAG_DM any longer. This should be fine as get_physical_address() only compares against MIPS_HFLAG_UM and MIPS_HFLAG_SM, neither of which should get set by compute_hflags() when MIPS_HFLAG_DM is set. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Decode microMIPS EVA load & store instructionsJames Hogan
Implement decoding of microMIPS EVA load and store instruction groups in the POOL31C pool. These use the same gen_ld(), gen_st(), gen_st_cond() helpers as the MIPS32 decoding, passing the equivalent MIPS32 opcodes as opc. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Decode MIPS32 EVA load & store instructionsJames Hogan
Implement decoding of MIPS32 EVA loads and stores. These access the user address space from kernel mode when implemented, so for each instruction we need to check that EVA is available from Config5.EVA & check for sufficient COP0 privilege (with the new check_eva()), and then override the mem_idx used for the operation. Unfortunately some Loongson 2E instructions use overlapping encodings, so we must be careful not to prevent those from being decoded when EVA is absent. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Prepare loads/stores for EVAJames Hogan
EVA load and store instructions access the user mode address map, so they need to use mem_idx of MIPS_HFLAG_UM. Update the various utility functions to allow mem_idx to be more easily overridden from the decoding logic. Specifically we add a mem_idx argument to the op_ld/st_* helpers used for atomics, and a mem_idx local variable to gen_ld(), gen_st(), and gen_st_cond(). Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Add CP0_Ebase.WG (write gate) supportJames Hogan
Add support for the CP0_EBase.WG bit, which allows upper bits to be written (bits 31:30 on MIPS32, or bits 63:30 on MIPS64), along with the CP0_Config5.CV bit to control whether the exception vector for Cache Error exceptions is forced into KSeg1. This is necessary on MIPS32 to support Segmentation Control and Enhanced Virtual Addressing (EVA) extensions (where KSeg1 addresses may not represent an unmapped uncached segment). It is also useful on MIPS64 to allow the exception base to reside in XKPhys, and possibly out of range of KSEG0 and KSEG1. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> [yongbok.kim@imgtec.com: minor changes] Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Weaken TLB flush on UX,SX,KX,ASID changesJames Hogan
There is no need to invalidate any shadow TLB entries when the ASID changes or when access to one of the 64-bit segments has been disabled, since doing so doesn't reveal to software whether any TLB entries have been evicted into the shadow half of the TLB. Therefore weaken the tlb flushes in these cases to only flush the QEMU TLB. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Tested-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Fix TLBWI shadow flush for EHINV,XI,RIJames Hogan
Writing specific TLB entries with TLBWI flushes shadow TLB entries unless an existing entry is having its access permissions upgraded. This is necessary as software would from then on expect the previous mapping in that entry to no longer be in effect (even if QEMU has quietly evicted it to the shadow TLB on a TLBWR). However it won't do this if only EHINV, XI, or RI bits have been set, even if that results in a reduction of permissions, so add the necessary checks to invoke the flush when these bits are set. Fixes: 2fb58b73746e ("target-mips: add RI and XI fields to TLB entry") Fixes: 9456c2fbcd82 ("target-mips: add TLBINV support") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Tested-by: Yongbok Kim <yongbok.kim@imgtec.com> [yongbok.kim@imgtec.com: cosmetic changes] Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Fix MIPS64 MFC0 UserLocal on BE hostJames Hogan
Using MFC0 to read CP0_UserLocal uses tcg_gen_ld32s_tl, however CP0_UserLocal is a target_ulong. On a big endian host with a MIPS64 target this reads and sign extends the more significant half of the 64-bit register. Fix this by using ld_tl to load the whole target_ulong and ext32s_tl to sign extend it, as done for various other target_ulong COP0 registers. Fixes: d279279e2b5c ("target-mips: implement UserLocal Register") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Petar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova
Needed to implement a target-agnostic gen_intermediate_code() in the future. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Benneé <alex.benee@linaro.org> Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-Id: <150002025498.22386.18051908483085660588.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19target/alpha: optimize gen_cvtlq() using deposit opPhilippe Mathieu-Daudé
Suggested-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170718045540.16322-10-f4bug@amsat.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19target/sparc: optimize gen_op_mulscc() using deposit opPhilippe Mathieu-Daudé
Suggested-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170718045540.16322-9-f4bug@amsat.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19target/sparc: optimize various functions using extract opPhilippe Mathieu-Daudé
Done with the Coccinelle semantic patch scripts/coccinelle/tcg_gen_extract.cocci. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19target/ppc: optimize various functions using extract opPhilippe Mathieu-Daudé
Done with the Coccinelle semantic patch scripts/coccinelle/tcg_gen_extract.cocci. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20170718045540.16322-6-f4bug@amsat.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19target/m68k: optimize bcd_flags() using extract opPhilippe Mathieu-Daudé
Done with the Coccinelle semantic patch scripts/coccinelle/tcg_gen_extract.cocci. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718045540.16322-5-f4bug@amsat.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19target/arm: optimize aarch32 rev16Aurelien Jarno
Use the same mask to avoid having to load two different constants, as suggested by Richard Henderson. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170516230159.4195-2-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19target/arm: Optimize aarch64 rev16Richard Henderson
It is much shorter to reverse all 4 half-words in parallel than extract, reverse, and deposit each in turn. Suggested-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19Merge remote-tracking branch 'remotes/rth/tags/pull-axp-20170718' into stagingPeter Maydell
Queued target/alpha patches # gpg: Signature made Wed 19 Jul 2017 05:42:55 BST # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-axp-20170718: target/alpha: Log temp leaks target/alpha: Fix temp leak in gen_fbcond target/alpha: Fix temp leak in gen_call_pal target/alpha: Fix temp leak in gen_mtpr target/alpha: Fix temp leak in gen_bcond target/alpha: Merge several flag bytes into ENV->FLAGS target/alpha: Copy tb->flags into DisasContext target/alpha: Remove amask from tb->flags Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-18target/alpha: Log temp leaksRichard Henderson
Tested-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-18target/alpha: Fix temp leak in gen_fbcondRichard Henderson
Tested-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-18target/alpha: Fix temp leak in gen_call_palRichard Henderson
Tested-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-18target/alpha: Fix temp leak in gen_mtprRichard Henderson
Tested-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-18target/alpha: Fix temp leak in gen_bcondRichard Henderson
Tested-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-18target/alpha: Merge several flag bytes into ENV->FLAGSRichard Henderson
The flags are arranged such that we can manipulate them either a whole, or as individual bytes. The computation within cpu_get_tb_cpu_state is now reduced to a single load and mask. Tested-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-18target/alpha: Copy tb->flags into DisasContextRichard Henderson
Tested-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-18target/alpha: Remove amask from tb->flagsRichard Henderson
This value is constant for the cpu and does not need to be stored within the TB. Tested-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-18target/sh4: Use tcg_gen_lookup_and_goto_ptrRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-28-rth@twiddle.net> [aurel32: fix whitespace] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Implement fsrraRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-27-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-09 14:41:13 +0000