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AgeCommit message (Expand)Author
2017-01-19hax: add Darwin supportVincent Palatin
2017-01-19Plumb the HAXM-based hardware acceleration supportVincent Palatin
2017-01-19target/i386: Add Intel HAX filesVincent Palatin
2017-01-19kvm: move cpu synchronization codeVincent Palatin
2017-01-19KVM: PPC: eliminate unnecessary duplicate constantsPaolo Bonzini
2017-01-18target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUsArtyom Tarasenko
2017-01-18target-sparc: store the UA2005 entries in sun4u formatArtyom Tarasenko
2017-01-18target-sparc: implement UA2005 ASI_MMU (0x21)Artyom Tarasenko
2017-01-18target-sparc: add more registers to dump_mmuArtyom Tarasenko
2017-01-18target-sparc: implement auto-demapping for UA2005 CPUsArtyom Tarasenko
2017-01-18target-sparc: allow 256M sized pagesArtyom Tarasenko
2017-01-18target-sparc: simplify ultrasparc_tsb_pointerArtyom Tarasenko
2017-01-18target-sparc: implement UA2005 TSB PointersArtyom Tarasenko
2017-01-18target-sparc: use SparcV9MMU type for sparc64 I/D-MMUsArtyom Tarasenko
2017-01-18target-sparc: replace the last tlb entry when no free entries leftArtyom Tarasenko
2017-01-18target-sparc: ignore writes to UA2005 CPU mondo queue registerArtyom Tarasenko
2017-01-18target-sparc: allow priveleged ASIs in hyperprivileged modeArtyom Tarasenko
2017-01-18target-sparc: use direct address translation in hyperprivileged modeArtyom Tarasenko
2017-01-18target-sparc: fix immediate UA2005 trapsArtyom Tarasenko
2017-01-18target-sparc: implement UA2005 rdhpstate and wrhpstate instructionsArtyom Tarasenko
2017-01-18target-sparc: implement UA2005 GL registerArtyom Tarasenko
2017-01-18target-sparc: implement UA2005 hypervisor trapsArtyom Tarasenko
2017-01-18target-sparc: hypervisor mode takes over nucleus modeArtyom Tarasenko
2017-01-18target-sparc: implement UltraSPARC-T1 Strand status ASRArtyom Tarasenko
2017-01-18target-sparc: implement UA2005 scratchpad registersArtyom Tarasenko
2017-01-18target-sparc: simplify replace_tlb_entry by using TTE_PGSIZEArtyom Tarasenko
2017-01-18target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor modeArtyom Tarasenko
2017-01-18target-sparc: add UltraSPARC T1 TLB #definesArtyom Tarasenko
2017-01-18target-sparc: add UA2005 TTE bit #definesArtyom Tarasenko
2017-01-18target-sparc: use explicit mmu register pointersArtyom Tarasenko
2017-01-18target-sparc: store cpu super- and hypervisor flags in TBArtyom Tarasenko
2017-01-18target-sparc: ignore MMU-faults if MMU is disabled in hypervisor modeArtyom Tarasenko
2017-01-16target-xtensa: implement RER/WER instructionsMax Filippov
2017-01-16Merge remote-tracking branch 'remotes/stsquad/tags/pull-tcg-common-tlb-reset-...Peter Maydell
2017-01-16stubs: remove stubs/kvm.cPaolo Bonzini
2017-01-16event_notifier: cleanups around event_notifier_set_handlerPaolo Bonzini
2017-01-16Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-2.9-pull-request' ...Peter Maydell
2017-01-15target/xtensa: implement MEMCTL SRMax Filippov
2017-01-15target/xtensa: fix ICACHE/DCACHE options detectionMax Filippov
2017-01-15target/xtensa: don't continue translation after exceptionMax Filippov
2017-01-15target/xtensa: support icountMax Filippov
2017-01-15target/xtensa: refactor CCOUNT/CCOMPAREMax Filippov
2017-01-15target/xtensa: implement RUNSTALLMax Filippov
2017-01-15target/xtensa: add static vectors selectionMax Filippov
2017-01-14target-m68k: increment/decrement with SPLaurent Vivier
2017-01-14target-m68k: CAS doesn't need aligned accessLaurent Vivier
2017-01-14target-m68k: manage pre-dec et post-inc in CASLaurent Vivier
2017-01-14target-m68k: fix gen_flush_flags()Laurent Vivier
2017-01-14target-m68k: fix bit operation with immediate valueLaurent Vivier
2017-01-14target-m68k: Implement bfffoRichard Henderson
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