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2018-06-29target/arm: Implement SVE floating-point arithmetic with immediateRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE floating-point compare vectorsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE scatter store vector immediateRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE first-fault gather loadsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE gather loadsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180627043328.11531-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE prefetchesRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE scatter storesRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE store vector/predicate registerRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE load and broadcast elementRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE Floating Point Accumulating Reduction GroupRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE FP Multiply-Add GroupRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180627043328.11531-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE floating-point arithmetic (predicated)Richard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE integer convert to floating-pointRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> [PMM: fixed typo] Message-id: 20180627043328.11531-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE load and broadcast quadwordRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE Memory Contiguous Store GroupRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE Contiguous Load, first-fault and no-faultRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180627043328.11531-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE Memory Contiguous Load GroupRichard Henderson
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* "info mtree" improvements (Alexey) * fake VPD block limits for SCSI passthrough (Daniel Barboza) * chardev and main loop fixes (Daniel Berrangé, Sergio, Stefan) * help fixes (Eduardo) * pc-dimm refactoring (David) * tests improvements and fixes (Emilio, Thomas) * SVM emulation fixes (Jan) * MemoryRegionCache fix (Eric) * WHPX improvements (Justin) * ESP cleanup (Mark) * -overcommit option (Michael) * qemu-pr-helper fixes (me) * "info pic" improvements for x86 (Peter) * x86 TCG emulation fixes (Richard) * KVM slot handling fix (Shannon) * Next round of deprecation (Thomas) * Windows dump format support (Viktor) # gpg: Signature made Fri 29 Jun 2018 12:03:05 BST # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (60 commits) tests/boot-serial: Do not delete the output file in case of errors hw/scsi: add VPD Block Limits emulation hw/scsi: centralize SG_IO calls into single function hw/scsi: cleanups before VPD BL emulation dump: add Windows live system dump dump: add fallback KDBG using in Windows dump dump: use system context in Windows dump dump: add Windows dump format to dump-guest-memory i386/cpu: make -cpu host support monitor/mwait kvm: support -overcommit cpu-pm=on|off hmp: obsolete "info ioapic" ioapic: support "info irq" ioapic: some proper indents when dump info ioapic: support "info pic" doc: another fix to "info pic" target-i386: Mark cpu_vmexit noreturn target-i386: Allow interrupt injection after STGI target-i386: Add NMI interception to SVM memory/hmp: Print owners/parents in "info mtree" WHPX: register for unrecognized MSR exits ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29i386/cpu: make -cpu host support monitor/mwaitMichael S. Tsirkin
When guest CPU PM is enabled, and with -cpu host, expose the host CPU MWAIT leaf in the CPUID so guest can make good PM decisions. Note: the result is 100% CPU utilization reported by host as host no longer knows that the CPU is halted. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20180622192148.178309-3-mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-28kvm: support -overcommit cpu-pm=on|offMichael S. Tsirkin
With this flag, kvm allows guest to control host CPU power state. This increases latency for other processes using same host CPU in an unpredictable way, but if decreases idle entry/exit times for the running VCPU, so to use it QEMU needs a hint about whether host CPU is overcommitted, hence the flag name. Follow-up patches will expose this capability to guest (using mwait leaf). Based on a patch by Wanpeng Li <kernellwp@gmail.com> . Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20180622192148.178309-2-mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-28hmp: obsolete "info ioapic"Peter Xu
Let's start to use "info pic" just like other platforms. For now we keep the command for a while so that old users can know what is the new command to use. Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20171229073104.3810-6-peterx@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-28target-i386: Mark cpu_vmexit noreturnJan Kiszka
It calls cpu_loop_exit in system emulation mode (and should never be called in user emulation mode). Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Message-Id: <6f4d44ffde55d074cbceb48309c1678600abad2f.1522769774.git.jan.kiszka@web.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-28target-i386: Allow interrupt injection after STGIJan Kiszka
We need to terminate the translation block after STGI so that pending interrupts can be injected. This fixes pending NMI injection for Jailhouse which uses "stgi; clgi" to open a brief injection window. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Message-Id: <37939b244dda0e9cccf96ce50f2b15df1e48315d.1522769774.git.jan.kiszka@web.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-28target-i386: Add NMI interception to SVMJan Kiszka
Check for SVM interception prior to injecting an NMI. Tested via the Jailhouse hypervisor. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Message-Id: <c65877e9a011ee4962931287e59f502c482b8d0b.1522769774.git.jan.kiszka@web.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-28WHPX: register for unrecognized MSR exitsJustin Terry (VM)
Some variations of Linux kernels end up accessing MSR's that the Windows Hypervisor doesn't implement which causes a GP to be returned to the guest. This fix registers QEMU for unimplemented MSR access and globally returns 0 on reads and ignores writes. This behavior is allows the Linux kernel to probe the MSR with a write/read/check sequence it does often without failing the access. Signed-off-by: Justin Terry (VM) <juterry@microsoft.com> Message-Id: <20180605221500.21674-2-juterry@microsoft.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-28WHPX workaround bug in OSVW handlingJustin Terry (VM)
Adds a workaround to an incorrect value setting CPUID Fn8000_0001_ECX[bit 9 OSVW] = 1. This can cause a guest linux kernel to panic when an issue to rdmsr C001_0140h returns 0. Disabling this feature correctly allows the guest to boot without accessing the osv workarounds. Signed-off-by: Justin Terry (VM) <juterry@microsoft.com> Message-Id: <20180605221500.21674-1-juterry@microsoft.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-28whpx: commit missing filePaolo Bonzini
Not included by mistake in commit 327fccb288976f95808efa968082fc9d4a9ced84. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-28target/i386: Fix BLSR and BLSIRichard Henderson
The implementation of these two instructions was swapped. At the same time, unify the setup of eflags for the insn group. Reported-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170712192902.15493-1-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-28move public invalidate APIs out of translate-all.{c,h}, clean upPaolo Bonzini
Place them in exec.c, exec-all.h and ram_addr.h. This removes knowledge of translate-all.h (which is an internal header) from several files outside accel/tcg and removes knowledge of AddressSpace from translate-all.c (as it only operates on ram_addr_t). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-28Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell
staging Pull request * Gracefully handle Linux AIO init failure # gpg: Signature made Wed 27 Jun 2018 15:48:28 BST # gpg: using RSA key 9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: linux-aio: properly bubble up errors from initialization compiler: add a sizeof_field() macro Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-27target/mips: Fix gdbstub to read/write 64 bit FP registersYongbok Kim
Fix gdbstub to read/write 64 bit FP registers Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Reviewed-by: Aleksandar Markovic <aleksandar.markovic@mips.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@mips.com>
2018-06-27target/mips: Fix data type for offsetYongbok Kim
Offset can be larger than 16 bit from nanoMIPS, and immediate field can be larger than 16 bits as well. Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <aleksandar.markovic@mips.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@mips.com>
2018-06-27target/mips: Update gen_flt_ldst()Yongbok Kim
Update gen_flt_ldst() in order to reuse the functions for nanoMIPS Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <aleksandar.markovic@mips.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@mips.com>
2018-06-27target/mips: Fix microMIPS on resetYongbok Kim
Fix to activate microMIPS on reset when Config3.ISA == {1, 3} Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Reviewed-by: Aleksandar Markovic <aleksandar.markovic@mips.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@mips.com>
2018-06-27target/mips: Raise a RI when given fs is n/a from CTC1Yongbok Kim
Fix to raise a Reserved Instruction exception when given fs is not available from CTC1. Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Reviewed-by: Aleksandar Markovic <aleksandar.markovic@mips.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@mips.com>
2018-06-27compiler: add a sizeof_field() macroStefan Hajnoczi
Determining the size of a field is useful when you don't have a struct variable handy. Open-coding this is ugly. This patch adds the sizeof_field() macro, which is similar to typeof_field(). Existing instances are updated to use the macro. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Message-id: 20180614164431.29305-1-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-06-26target/arm: Handle small regions in get_phys_addr_pmsav8()Peter Maydell
Allow ARMv8M to handle small MPU and SAU region sizes, by making get_phys_add_pmsav8() set the page size to the 1 if the MPU or SAU region covers less than a TARGET_PAGE_SIZE. We choose to use a size of 1 because it makes no difference to the core code, and avoids having to track both the base and limit for SAU and MPU and then convert into an artificially restricted "page size" that the core code will then ignore. Since the core TCG code can't handle execution from small MPU regions, we strip the exec permission from them so that any execution attempts will cause an MPU exception, rather than allowing it to end up with a cpu_abort() in get_page_addr_code(). (The previous code's intention was to make any small page be treated as having no permissions, but unfortunately errors in the implementation meant that it didn't behave that way. It's possible that some binaries using small regions were accidentally working with our old behaviour and won't now.) We also retain an existing bug, where we ignored the possibility that the SAU region might not cover the entire page, in the case of executable regions. This is necessary because some currently-working guest code images rely on being able to execute from addresses which are covered by a page-sized MPU region but a smaller SAU region. We can remove this workaround if we ever support execution from small regions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180620130619.11362-4-peter.maydell@linaro.org
2018-06-26target/arm: Set page (region) size in get_phys_addr_pmsav7()Peter Maydell
We want to handle small MPU region sizes for ARMv7M. To do this, make get_phys_addr_pmsav7() set the page size to the region size if it is less that TARGET_PAGE_SIZE, rather than working only in TARGET_PAGE_SIZE chunks. Since the core TCG code con't handle execution from small MPU regions, we strip the exec permission from them so that any execution attempts will cause an MPU exception, rather than allowing it to end up with a cpu_abort() in get_page_addr_code(). (The previous code's intention was to make any small page be treated as having no permissions, but unfortunately errors in the implementation meant that it didn't behave that way. It's possible that some binaries using small regions were accidentally working with our old behaviour and won't now.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180620130619.11362-3-peter.maydell@linaro.org
2018-06-22i386: Remove generic SMT thread checkBabu Moger
Remove generic non-intel check while validating hyperthreading support. Certain AMD CPUs can support hyperthreading now. CPU family with TOPOEXT feature can support hyperthreading now. Signed-off-by: Babu Moger <babu.moger@amd.com> Tested-by: Geoffrey McRae <geoff@hostfission.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1529443919-67509-4-git-send-email-babu.moger@amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-06-22i386: Enable TOPOEXT feature on AMD EPYC CPUBabu Moger
Enable TOPOEXT feature on EPYC CPU. This is required to support hyperthreading on VM guests. Also extend xlevel to 0x8000001E. Disable topoext on PC_COMPAT_2_12 and keep xlevel 0x8000000a. Signed-off-by: Babu Moger <babu.moger@amd.com> Message-Id: <1529443919-67509-3-git-send-email-babu.moger@amd.com> [ehabkost: Added EPYC-IBPB.xlevel to PC_COMPAT_2_12] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-06-22i386: Fix up the Node id for CPUID_8000_001EBabu Moger
This is part of topoext support. To keep the compatibility, it is better we support all the combination of nr_cores and nr_threads currently supported. By allowing more nr_cores and nr_threads, we might end up with more nodes than we can actually support with the real hardware. We need to fix up the node id to make this work. We can achieve this by shifting the socket_id bits left to address more nodes. Signed-off-by: Babu Moger <babu.moger@amd.com> Message-Id: <1529443919-67509-2-git-send-email-babu.moger@amd.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-06-22i386: Allow TOPOEXT to be enabled on older kernelsBabu Moger
Enabling TOPOEXT feature might cause compatibility issues if older kernels does not set this feature. Lets set this feature unconditionally. Signed-off-by: Babu Moger <babu.moger@amd.com> Message-Id: <1528939107-17193-2-git-send-email-babu.moger@amd.com> [ehabkost: rewrite comment and commit message] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-06-22i386: Define AMD's no SSB mitigation needed.Konrad Rzeszutek Wilk
AMD future CPUs expose a mechanism to tell the guest that the Speculative Store Bypass Disable is not needed and that the CPU is all good. This is exposed via the CPUID 8000_0008.EBX[26] bit. See 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf A copy of this document is available at https://bugzilla.kernel.org/show_bug.cgi?id=199889 Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Message-Id: <20180601153809.15259-3-konrad.wilk@oracle.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-06-22i386: define the AMD 'amd-ssbd' CPUID feature bitKonrad Rzeszutek Wilk
AMD future CPUs expose _two_ ways to utilize the Intel equivalant of the Speculative Store Bypass Disable. The first is via the virtualized VIRT_SPEC CTRL MSR (0xC001_011f) and the second is via the SPEC_CTRL MSR (0x48). The document titled: 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf gives priority of SPEC CTRL MSR over the VIRT SPEC CTRL MSR. A copy of this document is available at https://bugzilla.kernel.org/show_bug.cgi?id=199889 Anyhow, this means that on future AMD CPUs there will be _two_ ways to deal with SSBD. Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Message-Id: <20180601153809.15259-2-konrad.wilk@oracle.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-06-22i386: Remove ospke CPUID flag nameEduardo Habkost
OSPKE is not a static feature flag: it changes dynamically at runtime depending on CR4, and it was never configurable: KVM never returned OSPKE on GET_SUPPORTED_CPUID, and on TCG enables it automatically if CR4_PKE_MASK is set. Remove OSPKE from the feature name array so users don't try to configure it manually. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20180611203712.12086-1-ehabkost@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-06-22i386: Remove osxsave CPUID flag nameEduardo Habkost
OSXAVE is not a static feature flag: it changes dynamically at runtime depending on CR4, and it was never configurable: KVM never returned OSXSAVE on GET_SUPPORTED_CPUID, and it is not included in TCG_EXT_FEATURES. Remove OSXSAVE from the feature name array so users don't try to configure it manually. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20180611203855.13269-1-ehabkost@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-06-22i386: display known CPUID features linewrapped, in alphabetical orderDaniel P. Berrangé
When using '-cpu help' the list of CPUID features is grouped according to the internal low level CPUID grouping. The data printed results in very long lines too. This combines to make it hard for users to read the output and identify if QEMU knows about the feature they wish to use. This change gets rid of the grouping of features and treats all flags as single list. The list is sorted into alphabetical order and the printing with line wrapping at the 77th column. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20180606165527.17365-4-berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-06-22i386: improve sorting of CPU model namesDaniel P. Berrangé
The current list of CPU model names output by "-cpu help" is sorted alphabetically based on the internal QOM class name. The text that is displayed, however, uses the CPU model name, which is equivalent to the QOM class name, minus a suffix. Unfortunately that suffix has an effect on the sort ordering, for example, causing the various Broadwell variants to appear reversed: x86 486 x86 Broadwell-IBRS Intel Core Processor (Broadwell, IBRS) x86 Broadwell-noTSX-IBRS Intel Core Processor (Broadwell, no TSX, IBRS x86 Broadwell-noTSX Intel Core Processor (Broadwell, no TSX) x86 Broadwell Intel Core Processor (Broadwell) x86 Conroe Intel Celeron_4x0 (Conroe/Merom Class Core 2) By sorting on the actual CPU model name text that is displayed, the result is x86 486 x86 Broadwell Intel Core Processor (Broadwell) x86 Broadwell-IBRS Intel Core Processor (Broadwell, IBRS) x86 Broadwell-noTSX Intel Core Processor (Broadwell, no TSX) x86 Broadwell-noTSX-IBRS Intel Core Processor (Broadwell, no TSX, IBRS) x86 Conroe Intel Celeron_4x0 (Conroe/Merom Class Core 2) This requires extra string allocations during sorting, but this is not a concern given the usage scenario and the number of CPU models that exist. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20180606165527.17365-3-berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-06-22i386: improve alignment of CPU model listingDaniel P. Berrangé
Since the addition of the -IBRS CPU model variants, the descriptions shown by '-cpu help' are not well aligned, as several model names overflow the space allowed. Right aligning the CPU model names is also not attractive, because it obscures the common name prefixes of many models. The CPU model name field needs to be 4 characters larger, and be left aligned instead. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20180606165527.17365-2-berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-06-22i386: Add support for CPUID_8000_001E for AMDBabu Moger
Add support for cpuid leaf CPUID_8000_001E. Build the config that closely match the underlying hardware. Please refer to the Processor Programming Reference (PPR) for AMD Family 17h Model for more details. Signed-off-by: Babu Moger <babu.moger@amd.com> Message-Id: <1528498581-131037-2-git-send-email-babu.moger@amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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