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2018-09-25Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.1-20180925' ↵Peter Maydell
into staging ppc patch queue 2018-09-25 Here are the accumulated ppc target patches for the last several weeks. Highlights are: * A number of 40p / PReP cleanups * Preliminary irq rework on the pseries machine towards the new XIVE interrupt controller There are a few patches which make small changes to generic device and arm code as prerequisites to the 40p interrupt routing cleanup. They have acks from the relevant maintainers. # gpg: Signature made Tue 25 Sep 2018 08:00:06 BST # gpg: using RSA key 6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-3.1-20180925: 40p: add fixed IRQ routing for LSI SCSI device lsi53c895a: add optional external IRQ via qdev scsi: remove unused lsi53c895a_create() and lsi53c810_create() functions scsi: move lsi53c8xx_create() callers to lsi53c8xx_handle_legacy_cmdline() scsi: add lsi53c8xx_handle_legacy_cmdline() function sm501: Adjust endianness of pixel value in rectangle fill spapr_pci: add an extra 'nr_msis' argument to spapr_populate_pci_dt spapr: increase the size of the IRQ number space spapr: introduce a spapr_irq class 'nr_msis' attribute 40p: use OR gate to wire up raven PCI interrupts raven: some minor IRQ-related tidy-ups hw/ppc: on 40p machine, change default firmware to OpenBIOS target/ppc/cpu-models: Re-group the 970 CPUs together again Record history of ppcemb target in common.json Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25Merge remote-tracking branch 'remotes/xtensa/tags/20180918-xtensa' into stagingPeter Maydell
target/xtensa updates: - fix gdbstub register counts; - add big-endian core test_kc705_be; - convert to do_transaction_failed and add test for failed memory transactions; - fix couple FPU2000 bugs; - fix s32c1i implementation; - clean up exception handlers generation in xtensa tests; - add support for semihosting console input through a chardev. # gpg: Signature made Tue 18 Sep 2018 18:35:50 BST # gpg: using RSA key 51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <filippov@cadence.com>" # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20180918-xtensa: target/xtensa: support input from chardev console target/xtensa: fix s32c1i TCGMemOp flags tests/tcg/xtensa: only generate defined exception handlers tests/tcg/xtensa: move exception handlers to separate section target/xtensa: fix FPU2000 bugs tests/tcg/xtensa: add test for failed memory transactions target/xtensa: convert to do_transaction_failed target/xtensa: add test_kc705_be core target/xtensa: clean up gdbstub register handling target/xtensa: fix gdbstub register counts Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25target/ppc/cpu-models: Re-group the 970 CPUs together againThomas Huth
The addition of the POWER9 CPUs divided the entries for the 970 CPUs, which is a little bit confusing when you look at the code. So let's re-group the 970 CPUs together again, and since these chips have been based on the POWER4 processor, move them also in front of the POWER5 chips now. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-09-24Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.1-20180907' ↵Peter Maydell
into staging ppc patch queue 2018-09-07 Here's another pull request for qemu-3.1. No real theme here, just an assortment of various fixes. Probably the most notable thing is the removal of the ppcemb target which has been deprecated for some time now. # gpg: Signature made Fri 07 Sep 2018 08:30:02 BST # gpg: using RSA key 6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-3.1-20180907: target-ppc: Extend HWCAP2 bits for ISA 3.0 target/ppc/kvm: set vcpu as online/offline Fix a deadlock case in the CPU hotplug flow spapr: Correct reference count on spapr-cpu-core mac_newworld: implement custom FWPathProvider uninorth: add ofw-addr property to allow correct fw path generation mac_oldworld: implement custom FWPathProvider grackle: set device fw_name and address for correct fw path generation macio: add addr property to macio IDE object macio: add macio bus to help with fw path generation macio: move MACIOIDEState type declarations to macio.h spapr_pci: fix potential NULL pointer dereference spapr: fix leak of rev array ppc: Remove deprecated ppcemb target Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-24Merge remote-tracking branch ↵Peter Maydell
'remotes/alistair/tags/pull-riscv-pullreq-20180905' into staging A misc collection of RISC-V related patches for 3.1. # gpg: Signature made Wed 05 Sep 2018 23:06:55 BST # gpg: using RSA key 21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-pullreq-20180905: riscv: remove define cpu_init() hw/riscv/spike: Set the soc device tree node as a simple-bus hw/riscv/virtio: Set the soc device tree node as a simple-bus target/riscv: call gen_goto_tb on DISAS_TOO_MANY target/riscv: optimize indirect branches target/riscv: optimize cross-page direct jumps in softmmu RISC-V: Simplify riscv_cpu_local_irqs_pending RISC-V: Use atomic_cmpxchg to update PLIC bitmaps RISC-V: Improve page table walker spec compliance RISC-V: Update address bits to support sv39 and sv48 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-17target/xtensa: support input from chardev consoleMax Filippov
Complete xtensa-semi chardev console implementation: allow reading input characters from file descriptor 0 and call sys_select_one simcall on it. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-09-17target/xtensa: fix s32c1i TCGMemOp flagsMax Filippov
s32c1i must load and store value with target endianness, not host. This results in an infinite loop in atomic cmpxchg sequences when target endianness doesn't match host endianness. Fixes: 9fb40342d4b3 ("target/xtensa: support MTTCG") Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-09-17target/xtensa: fix FPU2000 bugsMax Filippov
- FPU2000 defines rfr and wfr opcodes, not rfr.s and wfr.s; - movcond.s uses incorrect operand in tcg_gen_movcond: in case the condition is not satisfied it must not change its argument 0. Fixes: c04e1692e3aa ("target/xtensa: extract FPU2000 opcode translators") Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-09-17target/xtensa: convert to do_transaction_failedMax Filippov
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-09-05riscv: remove define cpu_init()Igor Mammedov
cpu_init() was removed since 2.12, so drop the define that is now unused. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2018-09-05target/riscv: call gen_goto_tb on DISAS_TOO_MANYEmilio G. Cota
Performance impact of this and the previous commits, measured with the very-easy-to-cross-compile rv8-bench: https://github.com/rv8-io/rv8-bench Host: Intel(R) Core(TM) i7-4790K CPU @ 4.00GHz - Key: before: master after1,2,3: the 3 commits in this series (i.e. 3 is this commit) - User-mode: bench before after1 after2 after3 final speedup --------------------------------------------------------- aes 1.12s 1.12s 1.10s 1.00s 1.12 bigint 0.78s 0.78s 0.78s 0.78s 1 dhrystone 0.96s 0.97s 0.49s 0.49s 1.9591837 miniz 1.94s 1.94s 1.88s 1.86s 1.0430108 norx 0.51s 0.51s 0.49s 0.48s 1.0625 primes 0.85s 0.85s 0.84s 0.84s 1.0119048 qsort 4.87s 4.88s 1.86s 1.86s 2.6182796 sha512 0.76s 0.77s 0.64s 0.64s 1.1875 (after1 only applies to softmmu, so no surprises here) - Full-system (fedora): bench before after1 after2 after3 final speedup --------------------------------------------------------- aes 2.68s 2.54s 2.60s 2.34s 1.1452991 bigint 1.61s 1.56s 1.55s 1.64s 0.98170732 dhrystone 1.78s 1.67s 1.25s 1.24s 1.4354839 miniz 3.53s 3.35s 3.28s 3.35s 1.0537313 norx 1.13s 1.09s 1.07s 1.06s 1.0660377 primes 15.37s 15.41s 15.20s 15.37s 1 qsort 7.20s 6.71s 3.85s 3.96s 1.8181818 sha512 1.07s 1.04s 0.90s 0.90s 1.1888889 SoftMMU slows things down, so the numbers are less sensitive. Cross-page jumps improve things a little bit, though. Note that I'm not showing here averages, just results from a single run, so with primes there isn't much to worry about. Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2018-09-05target/riscv: optimize indirect branchesEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2018-09-05target/riscv: optimize cross-page direct jumps in softmmuEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2018-09-05target/ppc/kvm: set vcpu as online/offlineNikunj A Dadhania
Set the newly added register(KVM_REG_PPC_ONLINE) to indicate if the vcpu is online(1) or offline(0) KVM will use this information to set the RWMR register, which controls the PURR and SPURR accumulation. CC: paulus@samba.org Signed-off-by: Nikunj A Dadhania <nikunj@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-09-04RISC-V: Simplify riscv_cpu_local_irqs_pendingMichael Clark
This commit is intended to improve readability. There is no change to the logic. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2018-09-04RISC-V: Improve page table walker spec complianceMichael Clark
- Inline PTE_TABLE check for better readability - Change access checks from ternary operator to if - Improve readibility of User page U mode and SUM test - Disallow non U mode from fetching from User pages - Add reserved PTE flag check: W or W|X - Add misaligned PPN check - Set READ protection for PTE X flag and mstatus.mxr - Use memory_region_is_ram in pte update Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2018-09-04RISC-V: Update address bits to support sv39 and sv48Michael Clark
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2018-08-28target/s390x: use regular spaces in translate.cPavel Zbitskiy
In a few places translate.c contains non-breaking spaces (0xc2 0xa0) instead of regular ones (0x20): 7c 7c c2 a0 63 63 7c 7c 20 63 63 | | c c This confuses some text editors. Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com> Message-Id: <20180822144039.5796-2-pavel.zbitskiy@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-28target/s390x: fix PACK reading 1 byte less and writing 1 byte morePavel Zbitskiy
PACK fails on the test from the Principles of Operation: F1F2F3F4 becomes 0000234C instead of 0001234C due to an off-by-one error. Furthermore, it overwrites one extra byte to the left of F1. If len_dest is 0, then we only want to flip the 1st byte and never loop over the rest. Therefore, the loop condition should be > and not >=. If len_src is 1, then we should flip the 1st byte and pack the 2nd. Since len_src is already decremented before the loop, the first condition should be >=, and not >. Likewise for len_src == 2 and the second condition. Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com> Message-Id: <20180821025104.19604-7-pavel.zbitskiy@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-28target/s390x: add EX support for TRT and TRTRPavel Zbitskiy
Improves "b213c9f5: target/s390x: Implement TRTR" by introducing the intermediate functions, which are compatible with dx_helper type. Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com> Message-Id: <20180821025104.19604-6-pavel.zbitskiy@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-28target/s390x: fix IPM polluting irrelevant bitsPavel Zbitskiy
Suppose psw.mask=0x0000000080000000, cc=2, r1=0 and we do "ipm 1". This command must touch only bits 32-39, so the expected output is r1=0x20000000. However, currently qemu yields r1=0x20008000, because irrelevant parts of PSW leak into r1 during program mask transfer. Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com> Message-Id: <20180821025104.19604-5-pavel.zbitskiy@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-28target/s390x: fix CSST decoding and runtime alignment checkPavel Zbitskiy
CSST is defined as: C(0xc802, CSST, SSF, CASS, la1, a2, 0, 0, csst, 0) It means that the first parameter is handled by in1_la1(). in1_la1() fills addr1 field, and not in1. Furthermore, when extract32() is used for the alignment check, the third parameter should specify the number of trailing bits that must be 0. For FC these numbers are: FC=0 (word, 4 bytes): 2 FC=1 (double word, 8 bytes): 3 FC=2 (quad word, 16 bytes): 4 For SC these numbers correspond to the size: SC=0: 0 SC=1: 1 SC=2: 2 SC=3: 3 SC=4: 4 Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com> Message-Id: <20180821025104.19604-4-pavel.zbitskiy@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-28target/s390x: add BAL and BALR instructionsPavel Zbitskiy
These instructions are provided for compatibility purposes and are used only by old software, in the new code BAS and BASR are preferred. The difference between the old and new instruction exists only in the 24-bit mode. In addition, fix BAS polluting high 32 bits of the first operand in 24- and 31-bit addressing modes. Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com> Message-Id: <20180821025104.19604-3-pavel.zbitskiy@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-28ppc: Remove deprecated ppcemb targetThomas Huth
There is no known available OS for ppc around anymore that uses page sizes below 4k, so it does not make much sense that we keep wasting our time on building and testing the ppcemb-softmmu target. It has been deprecated since two releases, and nobody complained, so let's remove this now. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-08-24target/mips: Add definition of nanoMIPS I7200 CPUStefan Markovic
Add definition of the first nanoMIPS processor in QEMU. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Fix ERET/ERETNC behavior related to ADEL exceptionYongbok Kim
Fix ERET/ERETNC so that ADEL exception can be raised. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add updating BadInstr and BadInstrX for nanoMIPSStefan Markovic
Update BadInstr and BadInstrX registers for nanoMIPS. The same support for pre-nanoMIPS remains unimplemented. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add availability control via bit NMSDimitrije Nikolic
A set of nanoMIPS instructions is not available if Config5 bit NMS is set. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of DSP ASE for nanoMIPS - part 6Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 6. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of DSP ASE for nanoMIPS - part 5Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 5. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of DSP ASE for nanoMIPS - part 4Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 4. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of DSP ASE for nanoMIPS - part 3Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 3. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of DSP ASE for nanoMIPS - part 2Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 2. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of DSP ASE for nanoMIPS - part 1Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 1. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Implement MT ASE support for nanoMIPSStefan Markovic
Add emulation of MT ASE instructions for nanoMIPS. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Fix pre-nanoMIPS MT ASE instructions availability controlAleksandar Rikalo
Use bits from configuration registers for availability control of MT ASE instructions, rather than only ISA_MT bit in insn_flags. This is done by adding a field in hflags for MT bit, and adding functions check_mt() and check_cp0_mt(). Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of nanoMIPS 32-bit branch instructionsStefan Markovic
Add emulation of various flavors of nanoMIPS 32-bit branch instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Implement emulation of nanoMIPS LLWP/SCWP pairAleksandar Rikalo
Implement support for nanoMIPS LLWP/SCWP instructions. Beside adding core functionality of these instructions, this patch adds support for availability control via configuration bit XNP. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Dimitrije Nikolic <dnikolic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add CP0 Config3 and Config5 fields to DisasContext structureDimitrije Nikolic
Add CP0_Config3 and CP0_Config5 to DisasContext structure. This is needed for implementing availability control of various instructions. Reviewed-by: "Aleksandar Markovic <amarkovic@wavecomp.com>" Signed-off-by: "Aleksandar Markovic <amarkovic@wavecomp.com>"
2018-08-24target/mips: Add emulation of nanoMIPS 32-bit load and store instructionsYongbok Kim
Add emulation of various nanoMIPS load and store instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Implement emulation of nanoMIPS EXTW instructionJames Hogan
Implement emulation of nanoMIPS EXTW instruction. EXTW instruction is similar to the MIPS r6 ALIGN instruction, except that it counts the other way and in bits instead of bytes. We therefore generalise gen_align() function into a new gen_align_bits() function (which counts in bits instead of bytes and optimises when bits = size of the word), and implement gen_align() and a new gen_ext() based on that. Since we need to know the word size to check for when the number of bits == the word size, the opc argument is replaced with a wordsz argument (either 32 or 64). Signed-off-by: James Hogan <james.hogan@mips.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-08-24target/mips: Implement emulation of nanoMIPS ROTX instructionMatthew Fortune
Added a helper for ROTX based on the pseudocode from the architecture spec. This instraction was not present in previous MIPS instruction sets. Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-08-24target/mips: Add emulation of misc nanoMIPS instructions (p_lsx)Yongbok Kim
Add emulation of nanoMIPS instructions situated in pool p_lsx, and emulation of LSA instruction as well. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of misc nanoMIPS instructions (pool32axf)Yongbok Kim
Add emulation of misc nanoMIPS instructions situated in pool32axf. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of misc nanoMIPS instructions (pool32a0)Yongbok Kim
Add emulation of nanoMIPS instructions that are situated in pool32a0. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of nanoMIPS FP instructionsYongbok Kim
Add emulation of basic floating point arithmetic for nanoMIPS. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of nanoMIPS 48-bit instructionsYongbok Kim
Add emulation of LI48, ADDIU48, ADDIUGP48, ADDIUPC48, LWPC48, and SWPC48 instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREVYongbok Kim
Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of some common nanoMIPS 32-bit instructionsYongbok Kim
Add emulation of SIGRIE, SYSCALL, BREAK, SDBBP, ADDIU, ADDIUPC, ADDIUGP.W, LWGP, SWGP, ORI, XORI, ANDI, and other instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of nanoMIPS 16-bit save and restore instructionsStefan Markovic
Add emulation of SAVE16 and RESTORE.JRC16 instructions. Routines gen_save(), gen_restore(), and gen_adjust_sp() are provided to support this feature. This patch at the same time provides function gen_op_addr_addi(). This function will be used in emulation of some other nanoMIPS instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
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