Age | Commit message (Expand) | Author |
---|---|---|
2017-01-16 | target-xtensa: implement RER/WER instructions | Max Filippov |
2017-01-15 | target/xtensa: implement MEMCTL SR | Max Filippov |
2017-01-15 | target/xtensa: fix ICACHE/DCACHE options detection | Max Filippov |
2017-01-15 | target/xtensa: don't continue translation after exception | Max Filippov |
2017-01-15 | target/xtensa: support icount | Max Filippov |
2017-01-15 | target/xtensa: refactor CCOUNT/CCOMPARE | Max Filippov |
2017-01-15 | target/xtensa: implement RUNSTALL | Max Filippov |
2017-01-15 | target/xtensa: add static vectors selection | Max Filippov |
2016-12-22 | x86: implement la57 paging mode | Kirill A. Shutemov |
2016-12-22 | target-i386: Fix eflags.TF/#DB handling of syscall/sysret insns | Doug Evans |
2016-12-22 | kvmclock: reduce kvmclock difference on migration | Marcelo Tosatti |
2016-12-22 | x86: Fix x86_64 'g' packet response to gdb from 32-bit mode. | Doug Evans |
2016-12-22 | target-i386: Add Intel SHA_NI instruction support. | Yi Sun |
2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth |