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AgeCommit message (Expand)Author
2023-03-01target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfigDaniel Henrique Barboza
2023-03-01target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointersDaniel Henrique Barboza
2023-03-01target/riscv/csr.c: simplify mctr()Daniel Henrique Barboza
2023-03-01target/riscv/csr.c: use env_archcpu() in ctr()Daniel Henrique Barboza
2023-03-01Merge patch series "target/riscv: Add support for Svadu extension"Palmer Dabbelt
2023-03-01target/riscv: Export Svadu propertyWeiwei Li
2023-03-01target/riscv: Add *envcfg.HADE related check in address translationWeiwei Li
2023-03-01target/riscv: Add *envcfg.PBMTE related check in address translationWeiwei Li
2023-03-01target/riscv: Add csr support for svaduWeiwei Li
2023-03-01target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and h...Weiwei Li
2023-03-01target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc...Weiwei Li
2023-03-01target/riscv: Add support for Zicond extensionWeiwei Li
2023-03-01RISC-V: XTheadMemPair: Remove register restrictions for store-pairChristoph Müllner
2023-03-01target/riscv: Fix checking of whether instruciton at 'pc_next' spans pagesShaobo Song
2023-03-01Merge patch series "target/riscv: Various fixes to gdbstub and CSR access"Palmer Dabbelt
2023-03-01target/riscv: Group all predicate() routines togetherBin Meng
2023-03-01target/riscv: Drop priv level check in mseccfg predicate()Bin Meng
2023-03-01target/riscv: Allow debugger to access sstc CSRsBin Meng
2023-03-01target/riscv: Allow debugger to access {h, s}stateen CSRsBin Meng
2023-03-01target/riscv: Allow debugger to access seed CSRBin Meng
2023-03-01target/riscv: Allow debugger to access user timer and counter CSRsBin Meng
2023-03-01target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xmlBin Meng
2023-03-01target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate()Bin Meng
2023-03-01target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64Bin Meng
2023-03-01target/riscv: Simplify getting RISCVCPU pointer from envBin Meng
2023-03-01target/riscv: Simplify {read, write}_pmpcfg() a little bitBin Meng
2023-03-01target/riscv: Use 'bool' type for read_onlyBin Meng
2023-03-01target/riscv: Coding style fixes in csr.cBin Meng
2023-03-01target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabledBin Meng
2023-03-01target/riscv: gdbstub: Minor change for better readabilityBin Meng
2023-03-01target/riscv: Use g_assert() for the predicate() NULL checkBin Meng
2023-03-01target/riscv: Add some comments to clarify the priority policy of riscv_csrrw...Bin Meng
2023-03-01target/riscv: gdbstub: Check priv spec version before reporting CSRBin Meng
2023-03-01Merge patch series "target/riscv: Some updates to float point related extensi...Palmer Dabbelt
2023-03-01target/riscv: Expose properties for Zv* extensionsWeiwei Li
2023-03-01target/riscv: Simplify check for EEW = 64 in trans_rvv.c.incWeiwei Li
2023-03-01target/riscv: Fix check for vector load/store instructions when EEW=64Weiwei Li
2023-03-01target/riscv: Add support for Zvfh/zvfhmin extensionsWeiwei Li
2023-03-01target/riscv: Remove redundunt check for zve32f and zve64fWeiwei Li
2023-03-01target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.incWeiwei Li
2023-03-01target/riscv: Simplify check for Zve32f and Zve64fWeiwei Li
2023-03-01target/riscv: Indent fixes in cpu.cWeiwei Li
2023-03-01target/riscv: Add property check for Zvfh{min} extensionsWeiwei Li
2023-03-01target/riscv: Fix relationship between V, Zve*, F and DWeiwei Li
2023-03-01target/riscv: Add cfg properties for Zv* extensionsWeiwei Li
2023-03-01target/riscv: Simplify the check for Zfhmin and ZhinxminWeiwei Li
2023-03-01target/riscv: Fix the relationship between Zhinxmin and ZhinxWeiwei Li
2023-03-01target/riscv: Fix the relationship between Zfhmin and ZfhWeiwei Li
2023-03-01target/riscv/cpu: remove CPUArchState::features and friendsDaniel Henrique Barboza
2023-03-01target/riscv: remove RISCV_FEATURE_MMUDaniel Henrique Barboza
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