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QEMU is a generic and open source machine & userspace emulator and virtualizer
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2023-03-01
target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig
Daniel Henrique Barboza
2023-03-01
target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers
Daniel Henrique Barboza
2023-03-01
target/riscv/csr.c: simplify mctr()
Daniel Henrique Barboza
2023-03-01
target/riscv/csr.c: use env_archcpu() in ctr()
Daniel Henrique Barboza
2023-03-01
Merge patch series "target/riscv: Add support for Svadu extension"
Palmer Dabbelt
2023-03-01
target/riscv: Export Svadu property
Weiwei Li
2023-03-01
target/riscv: Add *envcfg.HADE related check in address translation
Weiwei Li
2023-03-01
target/riscv: Add *envcfg.PBMTE related check in address translation
Weiwei Li
2023-03-01
target/riscv: Add csr support for svadu
Weiwei Li
2023-03-01
target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and h...
Weiwei Li
2023-03-01
target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc...
Weiwei Li
2023-03-01
target/riscv: Add support for Zicond extension
Weiwei Li
2023-03-01
RISC-V: XTheadMemPair: Remove register restrictions for store-pair
Christoph Müllner
2023-03-01
target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages
Shaobo Song
2023-03-01
Merge patch series "target/riscv: Various fixes to gdbstub and CSR access"
Palmer Dabbelt
2023-03-01
target/riscv: Group all predicate() routines together
Bin Meng
2023-03-01
target/riscv: Drop priv level check in mseccfg predicate()
Bin Meng
2023-03-01
target/riscv: Allow debugger to access sstc CSRs
Bin Meng
2023-03-01
target/riscv: Allow debugger to access {h, s}stateen CSRs
Bin Meng
2023-03-01
target/riscv: Allow debugger to access seed CSR
Bin Meng
2023-03-01
target/riscv: Allow debugger to access user timer and counter CSRs
Bin Meng
2023-03-01
target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml
Bin Meng
2023-03-01
target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate()
Bin Meng
2023-03-01
target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64
Bin Meng
2023-03-01
target/riscv: Simplify getting RISCVCPU pointer from env
Bin Meng
2023-03-01
target/riscv: Simplify {read, write}_pmpcfg() a little bit
Bin Meng
2023-03-01
target/riscv: Use 'bool' type for read_only
Bin Meng
2023-03-01
target/riscv: Coding style fixes in csr.c
Bin Meng
2023-03-01
target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
Bin Meng
2023-03-01
target/riscv: gdbstub: Minor change for better readability
Bin Meng
2023-03-01
target/riscv: Use g_assert() for the predicate() NULL check
Bin Meng
2023-03-01
target/riscv: Add some comments to clarify the priority policy of riscv_csrrw...
Bin Meng
2023-03-01
target/riscv: gdbstub: Check priv spec version before reporting CSR
Bin Meng
2023-03-01
Merge patch series "target/riscv: Some updates to float point related extensi...
Palmer Dabbelt
2023-03-01
target/riscv: Expose properties for Zv* extensions
Weiwei Li
2023-03-01
target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc
Weiwei Li
2023-03-01
target/riscv: Fix check for vector load/store instructions when EEW=64
Weiwei Li
2023-03-01
target/riscv: Add support for Zvfh/zvfhmin extensions
Weiwei Li
2023-03-01
target/riscv: Remove redundunt check for zve32f and zve64f
Weiwei Li
2023-03-01
target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc
Weiwei Li
2023-03-01
target/riscv: Simplify check for Zve32f and Zve64f
Weiwei Li
2023-03-01
target/riscv: Indent fixes in cpu.c
Weiwei Li
2023-03-01
target/riscv: Add property check for Zvfh{min} extensions
Weiwei Li
2023-03-01
target/riscv: Fix relationship between V, Zve*, F and D
Weiwei Li
2023-03-01
target/riscv: Add cfg properties for Zv* extensions
Weiwei Li
2023-03-01
target/riscv: Simplify the check for Zfhmin and Zhinxmin
Weiwei Li
2023-03-01
target/riscv: Fix the relationship between Zhinxmin and Zhinx
Weiwei Li
2023-03-01
target/riscv: Fix the relationship between Zfhmin and Zfh
Weiwei Li
2023-03-01
target/riscv/cpu: remove CPUArchState::features and friends
Daniel Henrique Barboza
2023-03-01
target/riscv: remove RISCV_FEATURE_MMU
Daniel Henrique Barboza
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