aboutsummaryrefslogtreecommitdiff
path: root/target
AgeCommit message (Collapse)Author
2018-06-11target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insnRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180512050250.12774-10-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-06-11target/m68k: Improve ending TB at page boundariesRichard Henderson
Rather than limit total TB size to PAGE-32 bytes, end the TB when near the end of a page. This should provide proper semantics of SIGSEGV when executing near the end of a page. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180512050250.12774-9-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-06-11target/m68k: Convert to TranslatorOpsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180512050250.12774-8-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-06-11target/m68k: Convert to DisasContextBaseRichard Henderson
Removed ctx->insn_pc in favour of ctx->base.pc_next. Yes, it is annoying, but didn't want to waste its 4 bytes. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180512050250.12774-7-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-06-11target/m68k: Rename DISAS_UPDATE and gen_lookup_tbRichard Henderson
The name gen_lookup_tb is at odds with tcg_gen_lookup_and_goto_tb. For these cases, we do indeed want to exit back to the main loop. Similarly, DISAS_UPDATE performs no actual update, whereas DISAS_EXIT does what it says. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180512050250.12774-6-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-06-11target/m68k: Use lookup_and_goto_tb for DISAS_JUMPRichard Henderson
These are all indirect or out-of-page direct jumps. We can indirectly chain to the next TB without going back to the main loop. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180512050250.12774-5-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-06-11target/m68k: Remove DISAS_JUMP_NEXT as unusedRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180512050250.12774-4-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-06-11target/m68k: Replace DISAS_TB_JUMP with DISAS_NORETURNRichard Henderson
We have exited the TB after using goto_tb; there is no distinction from DISAS_NORETURN. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180512050250.12774-3-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-06-11target/m68k: Use DISAS_NORETURN for exceptionsRichard Henderson
The raise_exception helper does not return. Do not generate any code following that. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180512050250.12774-2-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-06-08target/xtensa: Add trailing '\n' to qemu_log() callsPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Message-id: 20180606152128.449-12-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-08RISC-V: Add trailing '\n' to qemu_log() callsPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180606152128.449-11-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-08target/m68k: Add trailing '\n' to qemu_log() callPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-id: 20180606152128.449-10-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-08target/arm: Add trailing '\n' to qemu_log() callsPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180606152128.449-9-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-05Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier2/tags/linux-user-for-3.0-pull-request' into staging move more data to arch specific files fix SPARC %tick replace strcpy() by g_strlcpy() in syscall.c # gpg: Signature made Mon 04 Jun 2018 16:19:44 BST # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/linux-user-for-3.0-pull-request: linux-user: remove useless #if linux-user: move hppa signal definitions to hppa/target_signal.h linux-user: move alpha signal definitions to alpha/target_signal.h linux-user: move openrisc signal definitions to openrisc/target_signal.h linux-user: move mips signal definitions to mips/target_signal.h linux-user: move sparc signal definitions to sparc/target_signal.h linux-user: move generic signal definitions to generic/signal.h linux-user: move get_sp_from_cpustate() to target_cpu.h linux-user: move sparc/sparc64 fcntl definitions to sparc/target_fcntl.h linux-user: move ppc fcntl definitions to ppc/target_fcntl.h linux-user: move mips/mips64 fcntl definitions to mips/target_fcntl.h linux-user: move arm/aarch64/m68k fcntl definitions to [arm|aarch64|m68k]/target_fcntl.h linux-user: move hppa fcntl definitions to hppa/target_fcntl.h linux-user: move alpha fcntl definitions to alpha/target_fcntl.h linux-user: move generic fcntl definitions to generic/fcntl.h linux-user: SPARC "rd %tick" can be used by user application syscall: replace strcpy() by g_strlcpy() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-04Merge remote-tracking branch 'remotes/rth/tags/tcg-next-pull-request' into ↵Peter Maydell
staging tcg-next queue # gpg: Signature made Sat 02 Jun 2018 00:12:42 BST # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/tcg-next-pull-request: tcg: Pass tb and index to tcg_gen_exit_tb separately Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-04linux-user: SPARC "rd %tick" can be used by user applicationLaurent Vivier
we have the same problem decribed in 7d6b1daedd ("linux-user, ppc: mftbl can be used by user application") for ppc in the case of sparc. When we use an application trying to resolve a name, it hangs in 0x00000000ff5dd40c: rd %tick, %o5 0x00000000ff5dd410: srlx %o5, 0x20, %o4 0x00000000ff5dd414: btst %o5, %g4 0x00000000ff5dd418: be %icc, 0xff5dd40c because %tick is staying at 0. As QEMU_CLOCK_VIRTUAL is not available in linux-user mode, simply use cpu_get_host_ticks() instead. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180528194812.31216-1-laurent@vivier.eu>
2018-06-01tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson
Do the cast to uintptr_t within the helper, so that the compiler can type check the pointer argument. We can also do some more sanity checking of the index argument. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-06-01Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* Linux header upgrade (Peter) * firmware.json definition (Laszlo) * IPMI migration fix (Corey) * QOM improvements (Alexey, Philippe, me) * Memory API cleanups (Jay, me, Tristan, Peter) * WHPX fixes and improvements (Lucian) * Chardev fixes (Marc-André) * IOMMU documentation improvements (Peter) * Coverity fixes (Peter, Philippe) * Include cleanup (Philippe) * -clock deprecation (Thomas) * Disable -sandbox unless CONFIG_SECCOMP (Yi Min Zhao) * Configurability improvements (me) # gpg: Signature made Fri 01 Jun 2018 17:42:13 BST # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (56 commits) hw: make virtio devices configurable via default-configs/ hw: allow compiling out SCSI memory: Make operations using MemoryRegionIoeventfd struct pass by pointer. char: Remove unwanted crlf conversion qdev: Remove DeviceClass::init() and ::exit() qdev: Simplify the SysBusDeviceClass::init path hw/i2c: Use DeviceClass::realize instead of I2CSlaveClass::init hw/i2c/smbus: Use DeviceClass::realize instead of SMBusDeviceClass::init target/i386/kvm.c: Remove compatibility shim for KVM_HINTS_REALTIME Update Linux headers to 4.17-rc6 target/i386/kvm.c: Handle renaming of KVM_HINTS_DEDICATED scripts/update-linux-headers: Handle kernel license no longer being one file scripts/update-linux-headers: Handle __aligned_u64 virtio-gpu-3d: Define VIRTIO_GPU_CAPSET_VIRGL2 elsewhere gdbstub: Prevent fd leakage docs/interop: add "firmware.json" ipmi: Use proper struct reference for KCS vmstate vmstate: Add a VSTRUCT type tcg: remove softfloat from --disable-tcg builds qemu-options: Mark the non-functional -clock option as deprecated ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-01target/i386/kvm.c: Remove compatibility shim for KVM_HINTS_REALTIMEPeter Maydell
Now we've updated our copy of the kernel headers we can remove the compatibility shim that handled KVM_HINTS_REALTIME not being defined. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180525132755.21839-7-peter.maydell@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-01target/i386/kvm.c: Handle renaming of KVM_HINTS_DEDICATEDPeter Maydell
In kernel header commit 633711e8287, the define KVM_HINTS_DEDICATED was renamed to KVM_HINTS_REALTIME. Work around this compatibility break by (a) using the new constant name, and (b) defining it if the headers don't. Part (b) can be removed once we've updated our copy of the kernel headers to a version that defines KVM_HINTS_REALTIME. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180525132755.21839-5-peter.maydell@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-01WHPX: fix some compiler warningsLucian Petrut
This patch fixes a few compiler warnings, especially in case of x86 targets, where the number of registers was not properly handled and could cause an overflow. Signed-off-by: Alessandro Pilotti <apilotti@cloudbasesolutions.com> Signed-off-by: Justin Terry (VM) <juterry@microsoft.com> Signed-off-by: Lucian Petrut <lpetrut@cloudbasesolutions.com> Message-Id: <1526405722-10887-3-git-send-email-lpetrut@cloudbasesolutions.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-01WHPX: dynamically load WHP librariesLucian Petrut
We're currently linking against import libraries of the WHP DLLs. By dynamically loading the libraries, we ensure that QEMU will work on previous Windows versions, where the WHP DLLs will be missing (assuming that WHP is not requested). Also, we're simplifying the build process, as we no longer require the import libraries. Signed-off-by: Alessandro Pilotti <apilotti@cloudbasesolutions.com> Signed-off-by: Justin Terry (VM) <juterry@microsoft.com> Signed-off-by: Lucian Petrut <lpetrut@cloudbasesolutions.com> Message-Id: <1526405722-10887-2-git-send-email-lpetrut@cloudbasesolutions.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-01nios2: do not include exec-all.h from cpu.hPaolo Bonzini
exec-all.h contains TCG-specific declarations, it should only be includer from helper C files. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-01target: Do not include "exec/exec-all.h" if it is not necessaryPhilippe Mathieu-Daudé
Code change produced with: $ git grep '#include "exec/exec-all.h"' | \ cut -d: -f-1 | \ xargs egrep -L "(cpu_address_space_init|cpu_loop_|tlb_|tb_|GETPC|singlestep|TranslationBlock)" | \ xargs sed -i.bak '/#include "exec\/exec-all.h"/d' Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180528232719.4721-10-f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-05-31target/hppa: Include "qemu/log.h" to use qemu_log()Philippe Mathieu-Daudé
Since his inception in 61766fe9e2d, this file uses the qemu_log() API from "qemu/log.h". Include it to allow further includes cleanup. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180528232719.4721-9-f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-05-31target/ppc: Include "exec/exec-all.h" which provides tlb_flush()Philippe Mathieu-Daudé
Since it inception this include uses tlb_flush() declared in "exec/exec-all.h". Include the other header to allow further includes cleanup. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180528232719.4721-8-f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-05-31target/xtensa: Include "qemu/timer.h" to use NANOSECONDS_PER_SECONDPhilippe Mathieu-Daudé
Since d0ce7e9cfc the dc232b structure uses the NANOSECONDS_PER_SECOND definition from "qemu/timer.h". Include it to allow further includes cleanup. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180528232719.4721-7-f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-05-31target/i386: Do not include "exec/ioport.h" if it is not necessaryPhilippe Mathieu-Daudé
Code change produced with: $ git grep '#include "exec/ioport.h"' target | \ cut -d: -f-1 | \ xargs egrep -Li "(portio|cpu_(in|out).\()" | \ xargs sed -i.bak '/#include "exec\/ioport.h"/d' Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180528232719.4721-6-f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-05-31target: Do not include "exec/address-spaces.h" if it is not necessaryPhilippe Mathieu-Daudé
Code change produced with: $ git grep '#include "exec/address-spaces.h"' target | \ cut -d: -f-1 | \ xargs egrep -L "(get_system_|address_space_)" | \ xargs sed -i.bak '/#include "exec\/address-spaces.h"/d' Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180528232719.4721-4-f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-05-31Make address_space_access_valid() take a MemTxAttrs argumentPeter Maydell
As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to address_space_access_valid(). Its callers either have an attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180521140402.23318-6-peter.maydell@linaro.org
2018-05-31Make address_space_map() take a MemTxAttrs argumentPeter Maydell
As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to address_space_map(). Its callers either have an attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180521140402.23318-5-peter.maydell@linaro.org
2018-05-31Make address_space_translate{, _cached}() take a MemTxAttrs argumentPeter Maydell
As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to address_space_translate() and address_space_translate_cached(). Callers either have an attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180521140402.23318-4-peter.maydell@linaro.org
2018-05-31Make tb_invalidate_phys_addr() take a MemTxAttrs argumentPeter Maydell
As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to tb_invalidate_phys_addr(). Its callers either have an attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180521140402.23318-3-peter.maydell@linaro.org
2018-05-31Correct CPACR reset value for v7 coresPeter Maydell
In commit f0aff255700 we made cpacr_write() enforce that some CPACR bits are RAZ/WI and some are RAO/WI for ARMv7 cores. Unfortunately we forgot to also update the register's reset value. The effect was that (a) a guest that read CPACR on reset would not see ones in the RAO bits, and (b) if you did a migration before the guest did a write to the CPACR then the migration would fail because the destination would enforce the RAO bits and then complain that they didn't match the zero value from the source. Implement reset for the CPACR using a custom reset function that just calls cpacr_write(), to avoid having to duplicate the logic for which bits are RAO. This bug would affect migration for TCG CPUs which are ARMv7 with VFP but without one of Neon or VFPv3. Reported-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180522173713.26282-1-peter.maydell@linaro.org
2018-05-31arm: fix malloc type mismatchPaolo Bonzini
cpregs_keys is an uint32_t* so the allocation should use uint32_t. g_new is even better because it is type-safe. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-31tcg: Fix helper function vs host abi for float16Richard Henderson
Depending on the host abi, float16, aka uint16_t, values are passed and returned either zero-extended in the host register or with garbage at the top of the host register. The tcg code generator has so far been assuming garbage, as that matches the x86 abi, but this is incorrect for other host abis. Further, target/arm has so far been assuming zero-extended results, so that it may store the 16-bit value into a 32-bit slot with the high 16-bits already clear. Rectify both problems by mapping "f16" in the helper definition to uint32_t instead of (a typedef for) uint16_t. This forces the host compiler to assume garbage in the upper 16 bits on input and to zero-extend the result on output. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20180522175629.24932-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-31target/arm: Honour FPCR.FZ in FRECPXPeter Maydell
The FRECPX instructions should (like most other floating point operations) honour the FPCR.FZ bit which specifies whether input denormals should be flushed to zero (or FZ16 for the half-precision version). We forgot to implement this, which doesn't affect the results (since the calculation doesn't actually care about the mantissa bits) but did mean we were failing to set the FPSR.IDC bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180521172712.19930-1-peter.maydell@linaro.org
2018-05-29Merge remote-tracking branch ↵Peter Maydell
'remotes/edgar/tags/edgar/xilinx-next-2018-05-29-v1.for-upstream' into staging Tag edgar/xilinx-next-2018-05-29-v1.for-upstream # gpg: Signature made Tue 29 May 2018 09:58:30 BST # gpg: using RSA key 29C596780F6BCA83 # gpg: Good signature from "Edgar E. Iglesias (Xilinx key) <edgar.iglesias@xilinx.com>" # gpg: aka "Edgar E. Iglesias <edgar.iglesias@gmail.com>" # Primary key fingerprint: AC44 FEDC 14F7 F1EB EDBF 4151 29C5 9678 0F6B CA83 * remotes/edgar/tags/edgar/xilinx-next-2018-05-29-v1.for-upstream: (38 commits) target-microblaze: Consolidate MMU enabled checks target-microblaze: cpu_mmu_index: Fixup indentation target-microblaze: Use tcg_gen_movcond in eval_cond_jmp target-microblaze: Convert env_btarget to i64 target-microblaze: Remove argument b in eval_cc() target-microblaze: Use table based condition-codes conversion target-microblaze: mmu: Cleanup debug log messages target-microblaze: Simplify address computation using tcg_gen_addi_i32() target-microblaze: Allow address sizes between 32 and 64 bits target-microblaze: Add support for extended access to TLBLO target-microblaze: dec_msr: Plug a temp leak target-microblaze: mmu: Add a configurable output address mask target-microblaze: mmu: Prepare for 64-bit addresses target-microblaze: mmu: Remove unused register state target-microblaze: mmu: Add R_TBLX_MISS macros target-microblaze: Implement MFSE EAR target-microblaze: Add Extended Addressing target-microblaze: Setup for 64bit addressing target-microblaze: Make special registers 64-bit target-microblaze: dec_msr: Fix MTS to FSR ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-29ppc: Rename 2.13 machines to 3.0Peter Maydell
Rename the 2.13 machines to match the number we're going to use for the next release. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Message-id: 20180522104000.9044-5-peter.maydell@linaro.org
2018-05-29target-microblaze: Consolidate MMU enabled checksEdgar E. Iglesias
Consolidate MMU enabled checks to cpu_mmu_index(). No functional changes. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: cpu_mmu_index: Fixup indentationEdgar E. Iglesias
Fixup the indentation of cpu_mmu_index in preparation for future edits. No functional changes. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Use tcg_gen_movcond in eval_cond_jmpEdgar E. Iglesias
Cleanup eval_cond_jmp to use tcg_gen_movcond_i64(). No functional change. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Convert env_btarget to i64Edgar E. Iglesias
Convert env_btarget to i64. No functional change. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Remove argument b in eval_cc()Edgar E. Iglesias
Remove argument b in eval_cc() as it is always set to zero. No functional change. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Use table based condition-codes conversionEdgar E. Iglesias
Use a table based conversion to map condition-codes between MicroBlaze ISA encoding and TCG. No functional change. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: mmu: Cleanup debug log messagesEdgar E. Iglesias
Cleanup debug log messages: * Avoid long 80+ character lines. * Remove D() macro and use qemu_log_mask. * Remove logs that are not very useful Suggested-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Simplify address computation using tcg_gen_addi_i32()Edgar E. Iglesias
Simplify address computation using tcg_gen_addi_i32(). tcg_gen_addi_i32() already optimizes the case when the immediate is zero. No functional change. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Allow address sizes between 32 and 64 bitsEdgar E. Iglesias
Allow address sizes between 32 and 64 bits. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Add support for extended access to TLBLOEdgar E. Iglesias
Add support for extended access to TLBLO's upper 32 bits. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: dec_msr: Plug a temp leakEdgar E. Iglesias
Plug a temp leak. Reported-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>