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2019-03-12spapr: Use CamelCase properlyDavid Gibson
The qemu coding standard is to use CamelCase for type and structure names, and the pseries code follows that... sort of. There are quite a lot of places where we bend the rules in order to preserve the capitalization of internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR". That was a bad idea - it frequently leads to names ending up with hard to read clusters of capital letters, and means they don't catch the eye as type identifiers, which is kind of the point of the CamelCase convention in the first place. In short, keeping type identifiers look like CamelCase is more important than preserving standard capitalization of internal "words". So, this patch renames a heap of spapr internal type names to a more standard CamelCase. In addition to case changes, we also make some other identifier renames: VIOsPAPR* -> SpaprVio* The reverse word ordering was only ever used to mitigate the capital cluster, so revert to the natural ordering. VIOsPAPRVTYDevice -> SpaprVioVty VIOsPAPRVLANDevice -> SpaprVioVlan Brevity, since the "Device" didn't add useful information sPAPRDRConnector -> SpaprDrc sPAPRDRConnectorClass -> SpaprDrcClass Brevity, and makes it clearer this is the same thing as a "DRC" mentioned in many other places in the code This is 100% a mechanical search-and-replace patch. It will, however, conflict with essentially any and all outstanding patches touching the spapr code. Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: Optimize x[sv]xsigdp using deposit_i64()Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20190309214255.9952-3-f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: Optimize xviexpdp() using deposit_i64()Philippe Mathieu-Daudé
The t0 tcg_temp register is now unused, remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20190309214255.9952-2-f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: add HV support for POWER9Cédric Le Goater
We now have enough support to boot a PowerNV machine with a POWER9 processor. Allow HV mode on POWER9. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190307223548.20516-16-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l,h}() and ↵Mark Cave-Ayland
set_cpu_vsr{l,h}() Now that all VSX registers are stored in host endian order, there is no need to go via different accessors depending upon the register number. Instead we introduce vsr64_offset() and use it directly from within get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}(). This also allows us to rewrite avr64_offset() and fpr_offset() in terms of the new vsr64_offset() function to more clearly express the relationship between the VSX, FPR and VMX registers, and also remove vsrl_offset() which is no longer required. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20190307180520.13868-8-mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: switch fpr/vsrl registers so all VSX registers are in host ↵Mark Cave-Ayland
endian order When VSX support was initially added, the fpr registers were added at offset 0 of the VSR register and the vsrl registers were added at offset 1. This is in contrast to the VMX registers (the last 32 VSX registers) which are stored in host-endian order. Switch the fpr/vsrl registers so that the lower 32 VSX registers are now also stored in host endian order to match the VMX registers. This ensures that TCG vector operations involving mixed VMX and VSX registers will function correctly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190307180520.13868-7-mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: improve avr64_offset() and use it to simplify ↵Mark Cave-Ayland
get_avr64()/set_avr64() By using the VsrD macro in avr64_offset() the same offset calculation can be used regardless of the host endian. This allows get_avr64() and set_avr64() to be simplified accordingly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20190307180520.13868-6-mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: introduce avr_full_offset() functionMark Cave-Ayland
All TCG vector operations require pointers to the base address of the vector rather than separate access to the top and bottom 64-bits. Convert the VMX TCG instructions to use a new avr_full_offset() function instead of avr64_offset() which can then itself be written as a simple wrapper onto vsr_full_offset(). This same function can also reused in cpu_avr_ptr() to avoid having more than one copy of the offset calculation logic. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20190307180520.13868-5-mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: move Vsr* macros from internal.h to cpu.hMark Cave-Ayland
It isn't possible to include internal.h from cpu.h so move the Vsr* macros into cpu.h alongside the other VMX/VSX register access functions. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20190307180520.13868-4-mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: introduce single vsrl_offset() functionMark Cave-Ayland
Instead of having multiple copies of the offset calculation logic, move it to a single vsrl_offset() function. This commit also renames the existing get_vsr()/set_vsr() functions to get_vsrl()/set_vsrl() which better describes their purpose. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190307180520.13868-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: introduce single fpr_offset() functionMark Cave-Ayland
Instead of having multiple copies of the offset calculation logic, move it to a single fpr_offset() function. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190307180520.13868-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc/spapr: Enable H_PAGE_INIT in-kernel handlingSuraj Jitindar Singh
The H_CALL H_PAGE_INIT can be used to zero or copy a page of guest memory. Enable the in-kernel H_PAGE_INIT handler. The in-kernel handler takes half the time to complete compared to handling the H_CALL in userspace. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Message-Id: <20190306060608.19935-1-sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: Refactor kvm_handle_debugFabiano Rosas
There are four scenarios being handled in this function: - single stepping - hardware breakpoints - software breakpoints - fallback (no debug supported) A future patch will add code to handle specific single step and software breakpoints cases so let's split each scenario into its own function now to avoid hurting readability. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-Id: <20190228225759.21328-5-farosas@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: Move handling of hardware breakpoints to a separate functionFabiano Rosas
This is in preparation for a refactoring of the kvm_handle_debug function in the next patch. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20190228225759.21328-4-farosas@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: Move exception vector offset computation into a functionFabiano Rosas
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-Id: <20190228225759.21328-2-farosas@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc/spapr: Add SPAPR_CAP_CCF_ASSISTSuraj Jitindar Singh
Introduce a new spapr_cap SPAPR_CAP_CCF_ASSIST to be used to indicate the requirement for a hw-assisted version of the count cache flush workaround. The count cache flush workaround is a software workaround which can be used to flush the count cache on context switch. Some revisions of hardware may have a hardware accelerated flush, in which case the software flush can be shortened. This cap is used to set the availability of such hardware acceleration for the count cache flush routine. The availability of such hardware acceleration is indicated by the H_CPU_CHAR_BCCTR_FLUSH_ASSIST flag being set in the characteristics returned from the KVM_PPC_GET_CPU_CHAR ioctl. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Message-Id: <20190301031912.28809-2-sjitindarsingh@gmail.com> [dwg: Small style fixes] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc/spapr: Add workaround option to SPAPR_CAP_IBSSuraj Jitindar Singh
The spapr_cap SPAPR_CAP_IBS is used to indicate the level of capability for mitigations for indirect branch speculation. Currently the available values are broken (default), fixed-ibs (fixed by serialising indirect branches) and fixed-ccd (fixed by diabling the count cache). Introduce a new value for this capability denoted workaround, meaning that software can work around the issue by flushing the count cache on context switch. This option is available if the hypervisor sets the H_CPU_BEHAV_FLUSH_COUNT_CACHE flag in the cpu behaviours returned from the KVM_PPC_GET_CPU_CHAR ioctl. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Message-Id: <20190301031912.28809-1-sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: Implement large decrementer support for KVMSuraj Jitindar Singh
Implement support to allow KVM guests to take advantage of the large decrementer introduced on POWER9 cpus. To determine if the host can support the requested large decrementer size, we check it matches that specified in the ibm,dec-bits device-tree property. We also need to enable it in KVM by setting the LPCR_LD bit in the LPCR. Note that to do this we need to try and set the bit, then read it back to check the host allowed us to set it, if so we can use it but if we were unable to set it the host cannot support it and we must not use the large decrementer. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190301024317.22137-3-sjitindarsingh@gmail.com> [dwg: Small style fixes] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: Implement large decrementer support for TCGSuraj Jitindar Singh
Prior to POWER9 the decrementer was a 32-bit register which decremented with each tick of the timebase. From POWER9 onwards the decrementer can be set to operate in a mode called large decrementer where it acts as a n-bit decrementing register which is visible as a 64-bit register, that is the value of the decrementer is sign extended to 64 bits (where n is implementation dependant). The mode in which the decrementer operates is controlled by the LPCR_LD bit in the logical paritition control register (LPCR). >From POWER9 onwards the HDEC (hypervisor decrementer) was enlarged to h-bits, also sign extended to 64 bits (where h is implementation dependant). Note this isn't configurable and is always enabled. On POWER9 the large decrementer and hdec are both 56 bits, as represented by the lrg_decr_bits cpu class property. Since they are the same size we only add one property for now, which could be extended in the case they ever differ in the future. We also add the lrg_decr_bits property for POWER5+/7/8 since it is used to determine the size of the hdec, which is only generated on the POWER5+ processor and later. On these processors it is 32 bits. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190301024317.22137-2-sjitindarsingh@gmail.com> [dwg: Small style fixes] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-11Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* allow building QEMU without TCG or KVM support (Anthony) * update AMD IOMMU copyright (David) * compilation fixes for GCC and BSDs (Alexey, David, Paolo, Philippe) * coalesced I/O bugfix (Jagannathan) * Processor Tracing cpuid fix (Luwei) * Kconfig fixes (Paolo, David) * Cleanups (Paolo, Wei) * PVH vs. multiboot fix (Stefano) * LSI bugfixes (Sven) * elf2dmp Coverity fix (Victor) * scsi-disk fix (Zhengui) * authorization support for chardev TLS (Daniel) # gpg: Signature made Mon 11 Mar 2019 16:12:00 GMT # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (31 commits) qemugdb: fix licensing chardev: add support for authorization for TLS clients qom: cpu: destroy work_mutex in cpu_common_finalize exec.c: refactor function flatview_add_to_dispatch() lsi: 810/895A are always little endian lsi: return dfifo value lsi: use SCSI phase names instead of numbers in trace lsi: use enum type for s->msg_action lsi: use enum type for s->waiting lsi: use ldn_le_p()/stn_le_p() scsi-disk: Fix crash if request is invaild or disk is no medium configure: Disable W^X on OpenBSD oslib-posix: Ignore fcntl("/dev/null", F_SETFL, O_NONBLOCK) failure accel: Allow to build QEMU without TCG or KVM support build: clean trace/generated-helpers.c build: remove unnecessary assignments from Makefile.target build: get rid of target-obj-y update copyright notice lsi: check if SIGP bit is already set in Wait reselect lsi: implement basic SBCL functionality ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-11i386: extended the cpuid_level when Intel PT is enabledLuwei Kang
Intel Processor Trace required CPUID[0x14] but the cpuid_level have no change when create a kvm guest with e.g. "-cpu qemu64,+intel-pt". Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Luwei Kang <luwei.kang@intel.com> Message-Id: <1548805979-12321-1-git-send-email-luwei.kang@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-03-11target-i386: add kvm stubs to user-mode emulatorsPaolo Bonzini
The CPUID code will call kvm_arch_get_supported_cpuid() and, even though it is undef kvm_enabled() so it never runs for user-mode emulators, sometimes clang will not optimize it out at -O0. That could be considered a compiler bug, however at -O0 we give it a pass and just add the stubs. Reported-by: Kamil Rytarowski <n54@gmx.com> Tested-by: Kamil Rytarowski <n54@gmx.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR UNPACK *David Hildenbrand
Combine all variant in a single handler. As source and destination have different element sizes, we can't use gvec expansion. Expand manually. Also watch out for overlapping source and destination registers. Use a safe evaluation order depending on the operation. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-33-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR STORE WITH LENGTHDavid Hildenbrand
Very similar to VECTOR LOAD WITH LENGTH, just the opposite direction. Properly probe write access before modifying memory. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-32-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR STORE MULTIPLEDavid Hildenbrand
Similar to VECTOR LOAD MULTIPLE, just the opposite direction. Probe write access first. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-31-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR STORE ELEMENTDavid Hildenbrand
As we only store one element, there is nothing to consider regarding exceptions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-30-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR STOREDavid Hildenbrand
Properly probe the whole access first. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-29-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Provide probe_write_access helperDavid Hildenbrand
Instead of checking e.g. the first access on every touched page, we should check the actual access, otherwise we might get false positives when Low Address Protection (LAP) is active. As probe_write() can only deal with accesses to one page, we have to loop. Use i64 for the length, although not needed - easier to reuse TCG temps we already have in the translation functions where this will be used. Also allow it to be used from other helpers. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-28-david@redhat.com> [CH: add missing page_check_range()] Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORDDavid Hildenbrand
Load both elements signed and store them into the two 64 bit elements. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-27-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR SELECTDavid Hildenbrand
Provide an implementation based on i64 and on real host vectors. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-26-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR SCATTER ELEMENTDavid Hildenbrand
Similar to VECTOR GATHER ELEMENT, but the other direction. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-25-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR REPLICATE IMMEDIATEDavid Hildenbrand
Like VECTOR REPLICATE, but the element to be replicated comes from an immediate. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-24-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR REPLICATEDavid Hildenbrand
Replicate via the special gvec helper. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-23-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATEDavid Hildenbrand
Read the whole input before modifying the destination vector. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-22-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR PERMUTEDavid Hildenbrand
Take care of overlying inputs and outputs by using a temporary vector. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-21-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR PACK *David Hildenbrand
This is a big one. Luckily we only have a limited set of such nasty instructions. We'll implement all variants with helpers, except when sources and the destination don't overlap for VECTOR PACK. Provide different helpers when the cc is to be modified. We'll return the cc then via env->cc_op. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-20-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR MERGE (HIGH|LOW)David Hildenbrand
We cannot use gvec expansion as source and destination elements are have different element numbers. So we'll expand using a fancy loop. Also, we have to take care of overlapping source and destination registers, therefore use a safe evaluation irder depending on the operation. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-19-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR LOAD WITH LENGTHDavid Hildenbrand
We can reuse the helper introduced along with VECTOR LOAD TO BLOCK BOUNDARY. We just have to take care of converting the highest index into a length. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-18-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINTDavid Hildenbrand
Fairly easy, just load from to gprs into a single vector. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-17-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GRDavid Hildenbrand
Very similar to VECTOR LOAD GR FROM VR ELEMENT, just the opposite direction. Also provide a fast path in case we don't care about the register content. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-16-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARYDavid Hildenbrand
Very similar to LOAD COUNT TO BLOCK BOUNDARY, but instead of only calculating, the actual vector is loaded. Use a temporary vector to not modify the real vector on exceptions. Initialize that one to zero, to not leak any data. Provide a fast path if we're loading a full vector. As we don't have gvec ool handlers for single vectors, just calculate the vector address manually. We can reuse the helper later on for VECTOR LOAD WITH LENGTH. In fact, we are going to name it "vll" right from the beginning, because that's a better match. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-15-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR LOAD MULTIPLEDavid Hildenbrand
Try to load the last element first. Access to the first element will be checked afterwards. This way, we can guarantee that the vector is not modified before we checked for all possible exceptions. (16 vectors cannot cross more than two pages) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-14-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERODavid Hildenbrand
Fairly easy, zero out the vector before we load the desired element. Load the element before touching the vector. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-13-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENTDavid Hildenbrand
To avoid an helper, we have to do the actual calculation of the element address (offset in cpu_env + cpu_env) manually. Factor that out into get_vec_element_ptr_i64(). The same logic will be reused for "VECTOR LOAD VR ELEMENT FROM GR". Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-12-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATEDavid Hildenbrand
Take care of properly sign-extending the immediate. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-11-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR LOAD ELEMENTDavid Hildenbrand
Fairly easy, load with desired size and store it into the right element. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR LOAD AND REPLICATEDavid Hildenbrand
We can use tcg_gen_gvec_dup_i64() to carry out the duplication. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-9-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR LOADDavid Hildenbrand
When loading from memory, load both elements into temps first before modifying the target vector Loading with strange alingment from the end of the address space will not properly wrap, we can ignore that for now. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR GENERATE MASKDavid Hildenbrand
Add gen_gvec_dupi() for handling duplication of immediates, so it can be reused later. Reviewed-by: Richard Henderson <richard.henderson@linaro.org Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR GENERATE BYTE MASKDavid Hildenbrand
Let's optimize it for the common cases (setting a vector to zero or all ones) - courtesy of Richard. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
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