aboutsummaryrefslogtreecommitdiff
path: root/target
AgeCommit message (Collapse)Author
2021-01-19target/arm/m_helper: Silence GCC 10 maybe-uninitialized errorPhilippe Mathieu-Daudé
When building with GCC 10.2 configured with --extra-cflags=-Os, we get: target/arm/m_helper.c: In function ‘arm_v7m_cpu_do_interrupt’: target/arm/m_helper.c:1811:16: error: ‘restore_s16_s31’ may be used uninitialized in this function [-Werror=maybe-uninitialized] 1811 | if (restore_s16_s31) { | ^ target/arm/m_helper.c:1350:10: note: ‘restore_s16_s31’ was declared here 1350 | bool restore_s16_s31; | ^~~~~~~~~~~~~~~ cc1: all warnings being treated as errors Initialize the 'restore_s16_s31' variable to silence the warning. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210119062739.589049-1-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: Update REV, PUNPK for pred_descRichard Henderson
Update all users of do_perm_pred2 for the new predicate descriptor field definitions. Cc: qemu-stable@nongnu.org Buglink: https://bugs.launchpad.net/bugs/1908551 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210113062650.593824-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: Update ZIP, UZP, TRN for pred_descRichard Henderson
Update all users of do_perm_pred3 for the new predicate descriptor field definitions. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210113062650.593824-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: Update PFIRST, PNEXT for pred_descRichard Henderson
These two were odd, in that do_pfirst_pnext passed the count of 64-bit words rather than bytes. Change to pass the standard pred_full_reg_size to avoid confusion. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210113062650.593824-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: Introduce PREDDESC field definitionsRichard Henderson
SVE predicate operations cannot use the "usual" simd_desc encoding, because the lengths are not a multiple of 8. But we were abusing the SIMD_* fields to store values anyway. This abuse broke when SIMD_OPRSZ_BITS was modified in e2e7168a214. Introduce a new set of field definitions for exclusive use of predicates, so that it is obvious what kind of predicate we are manipulating. To be used in future patches. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210113062650.593824-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: refactor vae1_tlbmask()Rémi Denis-Courmont
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-19-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: enable Secure EL2 in max CPURémi Denis-Courmont
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-18-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: Implement SCR_EL2.EEL2Rémi Denis-Courmont
This adds handling for the SCR_EL3.EEL2 bit. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Message-id: 20210112104511.36576-17-remi.denis.courmont@huawei.com [PMM: Applied fixes for review issues noted by RTH: - check for FEATURE_AARCH64 before checking sel2 isar feature - correct the commit message subject line] Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: revector to run-time pick target ELRémi Denis-Courmont
On ARMv8-A, accesses by 32-bit secure EL1 to monitor registers trap to the upper (64-bit) EL. With Secure EL2 support, we can no longer assume that that is always EL3, so make room for the value to be computed at run-time. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-16-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: set HPFAR_EL2.NS on secure stage 2 faultsRémi Denis-Courmont
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-15-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: secure stage 2 translation regimeRémi Denis-Courmont
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-14-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: generalize 2-stage page-walk conditionRémi Denis-Courmont
The stage_1_mmu_idx() already effectively keeps track of which translation regimes have two stages. Don't hard-code another test. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-13-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: translate NS bit in page-walksRémi Denis-Courmont
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-12-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: do S1_ptw_translate() before address space lookupRémi Denis-Courmont
In the secure stage 2 translation regime, the VSTCR.SW and VTCR.NSW bits can invert the secure flag for pagetable walks. This patchset allows S1_ptw_translate() to change the non-secure bit. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-11-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: handle VMID change in secure stateRémi Denis-Courmont
The VTTBR write callback so far assumes that the underlying VM lies in non-secure state. This handles the secure state scenario. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-10-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: add ARMv8.4-SEL2 system registersRémi Denis-Courmont
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-9-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: add MMU stage 1 for Secure EL2Rémi Denis-Courmont
This adds the MMU indices for EL2 stage 1 in secure state. To keep code contained, which is largelly identical between secure and non-secure modes, the MMU indices are reassigned. The new assignments provide a systematic pattern with a non-secure bit. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-8-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: add 64-bit S-EL2 to EL exception tableRémi Denis-Courmont
With the ARMv8.4-SEL2 extension, EL2 is a legal exception level in secure mode, though it can only be AArch64. This patch adds the target EL for exceptions from 64-bit S-EL2. It also fixes the target EL to EL2 when HCR.{A,F,I}MO are set in secure mode. Those values were never used in practice as the effective value of HCR was always 0 in secure mode. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-7-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: Define isar_feature function to test for presence of SEL2Rémi Denis-Courmont
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-6-remi.denis.courmont@huawei.com [PMM: tweaked commit message to match reduced scope of patch following rebase] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: factor MDCR_EL2 common handlingRémi Denis-Courmont
This adds a common helper to compute the effective value of MDCR_EL2. That is the actual value if EL2 is enabled in the current security context, or 0 elsewise. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-5-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: use arm_hcr_el2_eff() where applicableRémi Denis-Courmont
This will simplify accessing HCR conditionally in secure state. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-4-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: use arm_is_el2_enabled() where applicableRémi Denis-Courmont
Do not assume that EL2 is available in and only in non-secure context. That equivalence is broken by ARMv8.4-SEL2. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-3-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: add arm_is_el2_enabled() helperRémi Denis-Courmont
This checks if EL2 is enabled (meaning EL2 registers take effects) in the current security context. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-2-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: remove redundant testsRémi Denis-Courmont
In this context, the HCR value is the effective value, and thus is zero in secure mode. The tests for HCR.{F,I}MO are sufficient. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-1-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: Use object_property_add_bool for "sve" propertyRichard Henderson
The interface for object_property_add_bool is simpler, making the code easier to understand. Reviewed-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210111235740.462469-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: Add cpu properties to control pauthRichard Henderson
The crypto overhead of emulating pauth can be significant for some workloads. Add two boolean properties that allows the feature to be turned off, on with the architected algorithm, or on with an implementation defined algorithm. We need two intermediate booleans to control the state while parsing properties lest we clobber ID_AA64ISAR1 into an invalid intermediate state. Tested-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210111235740.462469-3-richard.henderson@linaro.org [PMM: fixed docs typo, tweaked text to clarify that the impdef algorithm is specific to QEMU] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19target/arm: Implement an IMPDEF pauth algorithmRichard Henderson
Without hardware acceleration, a cryptographically strong algorithm is too expensive for pauth_computepac. Even with hardware accel, we are not currently expecting to link the linux-user binaries to any crypto libraries, and doing so would generally make the --static build fail. So choose XXH64 as a reasonably quick and decent hash. Tested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210111235740.462469-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-18Merge remote-tracking branch ↵Peter Maydell
'remotes/stsquad/tags/pull-testing-and-misc-180121-2' into staging Testing, gdbstub and semihosting patches: - clean-ups to docker images - drop duplicate jobs from shippable - prettier tag generation (+gtags) - generate browsable source tree - more Travis->GitLab migrations - fix checkpatch to deal with commits - gate gdbstub tests on 8.3.1, expand tests - support Xfer:auxv:read gdb packet - better gdbstub cleanup - use GDB's SVE register layout - make arm-compat-semihosting common - add riscv semihosting support - add HEAPINFO, ELAPSED, TICKFREQ, TMPNAM and ISERROR to semihosting # gpg: Signature made Mon 18 Jan 2021 10:09:11 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-and-misc-180121-2: (30 commits) semihosting: Implement SYS_ISERROR semihosting: Implement SYS_TMPNAM semihosting: Implement SYS_ELAPSED and SYS_TICKFREQ riscv: Add semihosting support for user mode riscv: Add semihosting support semihosting: Support SYS_HEAPINFO when env->boot_info is not set semihosting: Change internal common-semi interfaces to use CPUState * semihosting: Change common-semi API to be architecture-independent semihosting: Move ARM semihosting code to shared directories target/arm: use official org.gnu.gdb.aarch64.sve layout for registers gdbstub: ensure we clean-up when terminated gdbstub: drop gdbserver_cleanup in favour of gdb_exit gdbstub: drop CPUEnv from gdb_exit() gdbstub: add support to Xfer:auxv:read: packet gdbstub: implement a softmmu based test Revert "tests/tcg/multiarch/Makefile.target: Disable run-gdbstub-sha1 test" configure: gate our use of GDB to 8.3.1 or above test/guest-debug: echo QEMU command as well scripts/checkpatch.pl: fix git-show invocation to include diffstat gitlab: migrate the minimal tools and unit tests from Travis ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # default-configs/targets/riscv32-linux-user.mak # default-configs/targets/riscv64-linux-user.mak
2021-01-18riscv: Add semihosting supportKeith Packard
Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210107170717.2098982-6-keithp@keithp.com> Message-Id: <20210108224256.2321-17-alex.bennee@linaro.org>
2021-01-18semihosting: Change common-semi API to be architecture-independentKeith Packard
The public API is now defined in hw/semihosting/common-semi.h. do_common_semihosting takes CPUState * instead of CPUARMState *. All internal functions have been renamed common_semi_ instead of arm_semi_ or arm_. Aside from the API change, there are no functional changes in this patch. Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210107170717.2098982-3-keithp@keithp.com> Message-Id: <20210108224256.2321-14-alex.bennee@linaro.org>
2021-01-18semihosting: Move ARM semihosting code to shared directoriesKeith Packard
This commit renames two files which provide ARM semihosting support so that they can be shared by other architectures: 1. target/arm/arm-semi.c -> hw/semihosting/common-semi.c 2. linux-user/arm/semihost.c -> linux-user/semihost.c The build system was modified use a new config variable, CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM softmmu and linux-user default configs. The contents of the source files has not been changed in this patch. Signed-off-by: Keith Packard <keithp@keithp.com> [AJB: rename arm-compat-semi, select SEMIHOSTING] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210107170717.2098982-2-keithp@keithp.com> Message-Id: <20210108224256.2321-13-alex.bennee@linaro.org>
2021-01-18target/arm: use official org.gnu.gdb.aarch64.sve layout for registersAlex Bennée
While GDB can work with any XML description given to it there is special handling for SVE registers on the GDB side which makes the users life a little better. The changes aren't that major and all the registers save the $vg reported the same. All that changes is: - report org.gnu.gdb.aarch64.sve - use gdb nomenclature for names and types - minor re-ordering of the types to match reference - re-enable ieee_half (as we know gdb supports it now) - $vg is now a 64 bit int - check $vN and $zN aliasing in test Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Luis Machado <luis.machado@linaro.org> Message-Id: <20210108224256.2321-11-alex.bennee@linaro.org>
2021-01-18gdbstub: drop CPUEnv from gdb_exit()Alex Bennée
gdb_exit() has never needed anything from env and I doubt we are going to start now. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210108224256.2321-8-alex.bennee@linaro.org>
2021-01-16target/riscv: Generate the GDB XML file for CSR registers dynamicallyBin Meng
At present QEMU RISC-V uses a hardcoded XML to report the feature "org.gnu.gdb.riscv.csr" [1]. There are two major issues with the approach being used currently: - The XML does not specify the "regnum" field of a CSR entry, hence consecutive numbers are used by the remote GDB client to access CSRs. In QEMU we have to maintain a map table to convert the GDB number to the hardware number which is error prone. - The XML contains some CSRs that QEMU does not implement at all, which causes an "E14" response sent to remote GDB client. Change to generate the CSR register list dynamically, based on the availability presented in the CSR function table. This new approach will reflect a correct list of CSRs that QEMU actually implements. [1] https://sourceware.org/gdb/current/onlinedocs/gdb/RISC_002dV-Features.html#RISC_002dV-Features Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210116054123.5457-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-01-16target/riscv: Add CSR name in the CSR function tableBin Meng
In preparation to generate the CSR register list for GDB stub dynamically, let's add the CSR name in the CSR function table. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1610427124-49887-3-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-01-16target/riscv: Make csr_ops[CSR_TABLE_SIZE] externalBin Meng
In preparation to generate the CSR register list for GDB stub dynamically, change csr_ops[] to non-static so that it can be referenced externally. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1610427124-49887-2-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-01-16target/riscv/pmp: Raise exception if no PMP entry is configuredAtish Patra
As per the privilege specification, any access from S/U mode should fail if no pmp region is configured. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201223192553.332508-1-atish.patra@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-01-16gdb: riscv: Add target descriptionSylvain Pelissier
Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response. Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210106204141.14027-1-sylvain.pelissier@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-01-14target/mips: Remove vendor specific CPU definitionsPhilippe Mathieu-Daudé
Vendor specific CPU definitions are not very useful. Use the ISA definitions instead, which are more helpful when looking at the various CPU definitions. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210112210152.2072996-4-f4bug@amsat.org>
2021-01-14target/mips: Remove CPU_NANOMIPS32 definitionPhilippe Mathieu-Daudé
nanoMIPS not a CPU, but an ISA. The nanoMIPS ISA is already defined as ISA_NANOMIPS32. Remove this incorrect definition and update the single CPU implementing it, the I7200. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210112210152.2072996-3-f4bug@amsat.org>
2021-01-14target/mips: Remove CPU_R5900 definitionPhilippe Mathieu-Daudé
Commit 823f2897bdd ("target/mips: Disable R5900 support") removed the single CPU using the CPU_R5900 definition. As it is unused, remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210112210152.2072996-2-f4bug@amsat.org>
2021-01-14target/mips: Convert Rel6 LL/SC opcodes to decodetreePhilippe Mathieu-Daudé
LL/SC opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-14-f4bug@amsat.org>
2021-01-14target/mips: Convert Rel6 LLD/SCD opcodes to decodetreePhilippe Mathieu-Daudé
LLD/SCD opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-13-f4bug@amsat.org>
2021-01-14target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetreePhilippe Mathieu-Daudé
LDL/LDR/SDL/SDR opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-12-f4bug@amsat.org>
2021-01-14target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetreePhilippe Mathieu-Daudé
LWLE/LWRE/SWLE/SWRE (EVA) opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-11-f4bug@amsat.org>
2021-01-14target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetreePhilippe Mathieu-Daudé
LWL/LWR/SWL/SWR opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-10-f4bug@amsat.org>
2021-01-14target/mips: Convert Rel6 CACHE/PREF opcodes to decodetreePhilippe Mathieu-Daudé
CACHE/PREF opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-9-f4bug@amsat.org>
2021-01-14target/mips: Convert Rel6 COP1X opcode to decodetreePhilippe Mathieu-Daudé
COP1x opcode has been removed from the Release 6. Add a single decodetree entry for it, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() call. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-8-f4bug@amsat.org>
2021-01-14target/mips: Convert Rel6 Special2 opcode to decodetreePhilippe Mathieu-Daudé
Special2 opcode have been removed from the Release 6. Add a single decodetree entry for all the opcode class, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() call. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-7-f4bug@amsat.org>
2021-01-14target/mips: Remove now unreachable LSA/DLSA opcodes codePhilippe Mathieu-Daudé
Since we switched to decodetree-generated processing, we can remove this now unreachable code. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-6-f4bug@amsat.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-02 01:39:13 +0000