Age | Commit message (Expand) | Author |
2020-09-01 | target/arm: Use macros instead of open-coding fp16 conversion helpers | Peter Maydell |
2020-09-01 | target/arm: Make VFP_CONV_FIX macros take separate float type and float size | Peter Maydell |
2020-09-01 | target/arm: Implement VFP fp16 VCVT between float and integer | Peter Maydell |
2020-09-01 | target/arm: Implement VFP fp16 VLDR and VSTR | Peter Maydell |
2020-09-01 | target/arm: Implement VFP fp16 VCMP | Peter Maydell |
2020-09-01 | target/arm: Implement VFP fp16 for VMOV immediate | Peter Maydell |
2020-09-01 | target/arm: Implement VFP fp16 for VABS, VNEG, VSQRT | Peter Maydell |
2020-09-01 | target/arm: Macroify uses of do_vfp_2op_sp() and do_vfp_2op_dp() | Peter Maydell |
2020-09-01 | target/arm: Implement VFP fp16 for fused-multiply-add | Peter Maydell |
2020-09-01 | target/arm: Macroify trans functions for VFMA, VFMS, VFNMA, VFNMS | Peter Maydell |
2020-09-01 | target/arm: Implement VFP fp16 VMLA, VMLS, VNMLS, VNMLA, VNMUL | Peter Maydell |
2020-09-01 | target/arm: Implement VFP fp16 for VFP_BINOP operations | Peter Maydell |
2020-09-01 | target/arm: Use correct ID register check for aa32_fp16_arith | Peter Maydell |
2020-09-01 | target/arm: Remove local definitions of float constants | Peter Maydell |
2020-08-28 | softfloat: Implement the full set of comparisons for float16 | Kito Cheng |
2020-08-28 | Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200828'... | Peter Maydell |
2020-08-28 | target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd | Richard Henderson |
2020-08-28 | target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimd | Richard Henderson |
2020-08-28 | target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd | Richard Henderson |
2020-08-28 | target/arm: Generalize inl_qrdmlah_* helper functions | Richard Henderson |
2020-08-28 | target/arm: Tidy SVE tszimm shift formats | Richard Henderson |
2020-08-28 | target/arm: Split out gen_gvec_ool_zz | Richard Henderson |
2020-08-28 | target/arm: Split out gen_gvec_ool_zzz | Richard Henderson |
2020-08-28 | target/arm: Split out gen_gvec_ool_zzp | Richard Henderson |
2020-08-28 | target/arm: Merge helper_sve_clr_* and helper_sve_movz_* | Richard Henderson |
2020-08-28 | target/arm: Split out gen_gvec_ool_zzzp | Richard Henderson |
2020-08-28 | target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp | Richard Henderson |
2020-08-28 | target/arm: Clean up 4-operand predicate expansion | Richard Henderson |
2020-08-28 | target/arm: Merge do_vector2_p into do_mov_p | Richard Henderson |
2020-08-28 | target/arm: Rearrange {sve,fp}_check_access assert | Richard Henderson |
2020-08-28 | target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn | Richard Henderson |
2020-08-28 | target/arm: Split out gen_gvec_fn_zz | Richard Henderson |
2020-08-28 | target/arm: Fill in the WnR syndrome bit in mte_check_fail | Richard Henderson |
2020-08-28 | target/arm: Pass the entire mte descriptor to mte_check_fail | Richard Henderson |
2020-08-28 | target/arm: Clarify HCR_EL2 ARMCPRegInfo type | Philippe Mathieu-Daudé |
2020-08-27 | hvf: Move HVFState typedef to hvf.h | Eduardo Habkost |
2020-08-25 | target/riscv: Support the Virtual Instruction fault | Alistair Francis |
2020-08-25 | target/riscv: Return the exception from invalid CSR accesses | Alistair Francis |
2020-08-25 | target/riscv: Support the v0.6 Hypervisor extension CRSs | Alistair Francis |
2020-08-25 | target/riscv: Only support little endian guests | Alistair Francis |
2020-08-25 | target/riscv: Only support a single VSXL length | Alistair Francis |
2020-08-25 | target/riscv: Update the CSRs to the v0.6 Hyp extension | Alistair Francis |
2020-08-25 | target/riscv: Update the Hypervisor trap return/entry | Alistair Francis |
2020-08-25 | target/riscv: Fix the interrupt cause code | Alistair Francis |
2020-08-25 | target/riscv: Convert MSTATUS MTL to GVA | Alistair Francis |
2020-08-25 | target/riscv: Don't allow guest to write to htinst | Alistair Francis |
2020-08-25 | target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions | Alistair Francis |
2020-08-25 | target/riscv: Allow generating hlv/hlvx/hsv instructions | Alistair Francis |
2020-08-25 | target/riscv: Allow setting a two-stage lookup in the virt status | Alistair Francis |
2020-08-24 | Merge remote-tracking branch 'remotes/xtensa/tags/20200821-xtensa' into staging | Peter Maydell |